70 research outputs found
Realization of Integrable Low- Voltage Companding Filters for Portable System Applications
Undoubtedly, today’s integrated electronic systems owe their remarkable performance
primarily to the rapid advancements of digital technology since 1970s. The various
important advantages of digital circuits are: its abstraction from the physical details of
the actual circuit implementation, its comparative insensitiveness to variations in the
manufacturing process, and the operating conditions besides allowing functional
complexity that would not be possible using analog technology. As a result, digital
circuits usually offer a more robust behaviour than their analog counterparts, though
often with area, power and speed drawbacks. Due to these and other benefits, analog
functionality has increasingly been replaced by digital implementations.
In spite of the advantages discussed above, analog components are far from
obsolete and continue to be key components of modern electronic systems. There is
a definite trend toward persistent and ubiquitous use of analog electronic circuits in
day-to-day life. Portable electronic gadgets, wireless communications and the
widespread application of RF tags are just a few examples of contemporary
developments. While all of these electronic systems are based on digital circuitry,
they heavily rely on analog components as interfaces to the real world. In fact, many
modern designs combine powerful digital systems and complementary analog
components on a single chip for cost and reliability reasons. Unfortunately, the design
of such systems-on-chip (SOC) suffers from the vastly different design styles of
analog and digital components. While mature synthesis tools are readily available for
digital designs, there is hardly any such support for analog designers apart from wellestablished
PSPICE-like circuit simulators. Consequently, though the analog part
usually occupies only a small fraction of the entire die area of an SOC, but its design
often constitutes a major bottleneck within the entire development process.
Integrated continuous-time active filters are the class of continuous-time or
analog circuits which are used in various applications like channel selection in radios,
anti-aliasing before sampling, and hearing aids etc. One of the figures of merit of a
filter is the dynamic range; this is the ratio of the largest to the smallest signal that can
be applied at the input of the filter while maintaining certain specified performance.
The dynamic range required in the filter varies with the application and is decided by
the variation in strength of the desired signal as well as that of unwanted signals that are to be rejected by the filter. It is well known that the power dissipation and the
capacitor area of an integrated active filter increases in proportion to its dynamic
range. This situation is incompatible with the needs of integrated systems, especially
battery operated ones. In addition to this fundamental dependence of power dissipation
on dynamic range, the design of integrated active filters is further complicated by the
reduction of supply voltage of integrated circuits imposed by the scaling down of
technologies to attain twin objective of higher speed and lower power consumption in
digital circuits. The reduction in power consumption with decreasing supply voltage
does not apply to analog circuits. In fact, considerable innovation is required with a
reduced supply voltage even to avoid increasing power consumption for a given signal
to noise ratio (S/N). These aspects pose a great hurdle to the active filter designer.
A technique which has attracted the attention of circuit designers as a possible
route to filters with higher dynamic range per unit power consumption is
“companding”. Companding (compression-expansion) filters are a very promising
subclass of continuous-time analog filters, where the input (linear) signal is initially
compressed before it will be handled by the core (non-linear) system. In order to
preserve the linear operation of the whole system, the non-linear signal produced by
the core system is converted back to a linear output signal by employing an
appropriate output stage. The required compression and expansion operations are
performed by employing bipolar transistors in active region or MOS transistors in
weak inversion; the systems thus derived are known as logarithmic-domain (logdomain)
systems. In case MOS transistors operated in saturation region are employed,
the derived structures are known as Square-root domain systems. Finally, the third
class of companding filters can also be obtained by employing bipolar transistors in
active region or MOS transistors in weak inversion; the derived systems are known as
Sinh-domain systems. During the last several years, a significant research effort has been already
carried out in the area of companding circuits. This is due to the fact that their main
advantages are the capability for operation in low-voltage environment and large
dynamic range originated from their companding nature, electronic tunability of the
frequency characteristics, absence of resistors and the potential for operations in varied
frequency regions.Thus, it is obvious that companding filters can be employed for implementing
high-performance analog signal processing in diverse frequency ranges. For example,
companding filters could be used for realizing subsystems in: xDSL modems, disk
drive read channels, biomedical electronics, Bluetooth/ZigBee applications, phaselocked
loops, FM stereo demodulator, touch-tone telephone tone decoder and
crossover network used in a three-way high-fidelity loudspeaker etc.
A number of design methods for companding filters and their building blocks
have been introduced in the literature. Most of the proposed filter structures operate
either above 1.5V or under symmetrical (1.5V) power supplies. According to data that
provides information about the near future of semiconductor technology, International
Technology Roadmap for Semiconductors (ITRS), in 2013, the supply voltage of digital
circuits in 32 nm technology will be 0.5 V. Therefore, the trend for the implementation of
analog integrated circuits is the usage of low-voltage building blocks that use a single
0.5-1.5V power supply.
Therefore, the present investigation was primarily concerned with the study and
design of low voltage and low power Companding filters. The work includes the
study about: the building blocks required in implementing low voltage and low power
Companding filters; the techniques used to realize low voltage and low power
Companding filters and their various areas of application.
Various novel low voltage and low power Companding filter designs have been
developed and studied for their characteristics to be applied in a particular portable
area of application. The developed designs include the N-th order universal
Companding filter designs, which have been reported first time in the open literature.
Further, an endeavor has been made to design Companding filters with orthogonal
tuning of performance parameters so that the designs can be simultaneously used for
various features. The salient features of each of the developed circuit are described.
Electronic tunability is one of the major features of all of the designs. Use of
grounded capacitors and resistorless designs in all the cases makes the designs suitable
for IC technology. All the designs operate in a low-voltage and low-power
environment essential for portable system applications.
Unless specified otherwise, all the investigations on these designs are based on the
PSPICE simulations using model parameters of the NR100N bipolar transistors and BSIM 0.35μm/TSMC 0.25μm /TSMC 0.18μm CMOS process MOS transistors. The
performance of each circuit has been validated by comparing the characteristics
obtained using simulation with the results present in the open literature.
The proposed designs could not be realized in silicon due to non-availability of
foundry facility at the place of study. An effort has already been started to realize
some of the designs in silicon and check their applicability in practical circuits. At the
basic level, one of the proposed Companding filter designs was implemented using the
commercially available transistor array ICs (LM3046N) and was found to verify the
theoretical predictions obtained from the simulation results
Advances in Solid State Circuit Technologies
This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields
The design of active resistors and transductors in a CMOS technology
Merged with duplicate record 10026.1/2618 on 07.20.2017 by CS (TIS)This thesis surveys linearisation techniques for implementing monolithic MOS
active resistors and transconductors, and investigates the design of linear tunable
resistors and transconductors. Improving linearity and tunability in the presence
of non-ideal factors such as bulk modulation, mobility-degradation effects and mismatch
of transistors is a principal objective. A family of new non-saturation-mode
resistors and two novel saturation-mode transconductors are developed. Where
possible, approximate analytical expressions are derived to explain the principles
of operation. Performance comparisons of the new structures are made with other
well-known circuits and their relative advantages and disadvantages evaluated.
Experimental and simulation results are presented which validate the proposed
linearisation techniques. It is shown that the proposed family of resistors offers
improved linearity whilst the transconductors combine extended tunability with
low distortion. Continuous-time filter examples are given to demonstrate the
potential of these circuits for application in analogue signal-processing tasks.GEC Plessey Semiconductors, Plymout
Power-efficient current-mode analog circuits for highly integrated ultra low power wireless transceivers
In this thesis, current-mode low-voltage and low-power techniques have been applied to implement novel analog circuits for zero-IF receiver backend design, focusing on amplification, filtering and detection stages. The structure of the thesis follows a bottom-up scheme: basic techniques at device level for low voltage low power operation are proposed in the first place, followed by novel circuit topologies at cell level, and finally the achievement of new designs at system level.
At device level the main contribution of this work is the employment of Floating-Gate (FG) and Quasi-Floating-Gate (QFG) transistors in order to reduce the power consumption. New current-mode basic topologies are proposed at cell level: current mirrors and current conveyors. Different topologies for low-power or high performance operation are shown, being these circuits the base for the system level designs.
At system level, novel current-mode amplification, filtering and detection stages using the former mentioned basic cells are proposed. The presented current-mode filter makes use of companding techniques to achieve high dynamic range and very low power consumption with for a very wide tuning range. The amplification stage avoids gain bandwidth product achieving a constant bandwidth for different gain configurations using a non-linear active feedback network, which also makes possible to tune the bandwidth. Finally, the proposed current zero-crossing detector represents a very power efficient mixed signal detector for phase modulations. All these designs contribute to the design of very low power compact Zero-IF wireless receivers.
The proposed circuits have been fabricated using a 0.5μm double-poly n-well CMOS technology, and the corresponding measurement results are provided and analyzed to validate their operation. On top of that, theoretical analysis has been done to fully explore the potential of the resulting circuits and systems in the scenario of low-power low-voltage applications.Programa Oficial de Doctorado en Tecnologías de las Comunicaciones (RD 1393/2007)Komunikazioen Teknologietako Doktoretza Programa Ofiziala (ED 1393/2007
Low-Power and Programmable Analog Circuitry for Wireless Sensors
Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments. One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment. In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors. The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device\u27s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode. This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks. Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits
Low Power Filtering Techniques for Wideband and Wireless Applications
This dissertation presents design and implementation of continuous time analog
filters for two specific applications: wideband analog systems such as disk drive channel
and low-power wireless applications. Specific focus has been techniques that reduce the
power requirements of the overall system either through improvement in architecture or
efficiency of the analog building blocks.
The first problem that this dissertation addresses is the implementation of
wideband filters with high equalization gain. An efficient architecture that realizes
equalization zeros by combining available transfer functions associated with a
biquadratic cell is proposed. A 330MHz, 5th order Gm-C lowpass Butterworth filter with
24dB boost is designed using the proposed architecture. The prototype fabricated in
standard 0.35um CMOS process shows -41dB of IM3 for 250mV peak to peak swing
with 8.6mW/pole of power dissipation. Also, an LC prototype implemented using
similar architecture is discussed in brief. It is shown that, for practical range of frequency and SNR, LC based design is more power efficient than a Gm-C one, though
at the cost of much larger area.
Secondly, a complementary current mirror based building block is proposed,
which pushes the limits imposed by conventional transconductors on the powerefficiency
of Gm-C filters. Signal processing through complementary devices provides
good linearity and Gm/Id efficiency and is shown to improve power efficiency by nearly
7 times. A current-mode 4th order Butterworth filter is designed, in 0.13um UMC
technology, using the proposed building. It provides 54.2dB IM3 and 55dB SNR in
1.3GHz bandwidth while consuming as low as 24mW of power. All CMOS filter
realization occupies a relatively small area and is well suited for integration in deep
submicron technologies.
Thirdly, a 20MHz, 68dB dynamic range active RC filter is presented. This filter
is designed for a ten bit continuous time sigma delta ADC architecture developed
specifically for fine-line CMOS technologies. Inverter based amplification and a
common mode feedback for such amplifiers are discussed. The filter consumes 5mW of
power and occupies an area of 0.07 mm2
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