An investigation of error correcting techniques for OMV data

Papers on the following topics are presented: considerations of testing the Orbital Maneuvering Vehicle (OMV) system with CLASS; OMV CLASS test results (first go around); equivalent system gain available from R-S encoding versus a desire to lower the power amplifier from 25 watts to 20 watts for OMV; command word acceptance/rejection rates for OMV; a memo concerning energy-to-noise ratio for the Viterbi-BSC Channel and the impact of Manchester coding loss; and an investigation of error correcting techniques for OMV and Advanced X-ray Astrophysics Facility (AXAF)

Shuttle S-band communications technical concepts

Using the S-band communications system, shuttle orbiter can communicate directly with the Earth via the Ground Spaceflight Tracking and Data Network (GSTDN) or via the Tracking and Data Relay Satellite System (TDRSS). The S-band frequencies provide the primary links for direct Earth and TDRSS communications during all launch and entry/landing phases of shuttle missions. On orbit, S-band links are used when TDRSS Ku-band is not available, when conditions require orbiter attitudes unfavorable to Ku-band communications, or when the payload bay doors are closed. the S-band communications functional requirements, the orbiter hardware configuration, and the NASA S-band communications network are described. The requirements and implementation concepts which resulted in techniques for shuttle S-band hardware development discussed include: (1) digital voice delta modulation; (2) convolutional coding/Viterbi decoding; (3) critical modulation index for phase modulation using a Costas loop (phase-shift keying) receiver; (4) optimum digital data modulation parameters for continuous-wave frequency modulation; (5) intermodulation effects of subcarrier ranging and time-division multiplexing data channels; (6) radiofrequency coverage; and (7) despreading techniques under poor signal-to-noise conditions. Channel performance is reviewed

Engineering evaluations and studies. Volume 3: Exhibit C

High rate multiplexes asymmetry and jitter, data-dependent amplitude variations, and transition density are discussed

[[alternative]]Design of Robust System and Smart Network for Broadband Optical Metro and Access Networks(I)

計畫編號：NSC94-2213-E032-005研究期間：200508~200607研究經費：660,000[[abstract]]Part A: 提出一寬頻光都會與接取網路之強健系統設計，利用強健控制器來使雷射波長更穩定縮短穩定時間且 利用參數最佳化設計來調整網路效能(包括溫度變化與元件的老化等)，也針對所用的強健控制系統作 硬體的實現來驗證我們所設計的控制器。 (1) 強健控制器設計 (2) 波長穩定控制器之分析與設計 (3) 網路元件之強健動態控制系統分析 (4) 強健控制器最佳化設計 (5) 波長穩定控制器之最佳化分析與設計 (6) 網路元件之強健動態控制系統設計 (7) 強健控制器硬體設計 (8) 波長穩定控制器之實際參數分析與設計 (9) 網路元件之強健動態控制最佳化 Part B: 提出由基因演算法來對每個網路元件作動態控制器設計，針對光接取網路提出基因演算法加速裝置將 網路作最佳化的調整使網路效能達最佳化。另一方面，我們也對寬頻光都會與接取網路之智慧網路設 計增加網路的效能。 (1) 基因演算法之最佳化控制設計 (2) 基因演算法加速裝置之光接取網路設計 (3) 智慧網路之光接取網路設計 (4) 基因演算法之動態控制設計 (5) 管線型基因演算法加速裝置之光接取網路設計 (6) 智慧網路之光接取網路設計 (7) 基因演算法之光接取網路動態控制設計 (8) 管線型基因演算法加速裝置硬體設計 (9) 智慧網路之光接取網路最佳化設計 Part C: 將強健系統與智慧網路套用至PON(Passive Optical Network) 的系統中來驗證， 包括針對 WDM-PON(Wavelength Division Multiplexing-PON) 與CDMA-PON (Code Division Multiple Access-PON)的最佳化設計，另一方面也針對WDM-PON與CDMA-PON的MAC(Media Access Control) 做規劃與設計(包括封包的設計等)，利用GA 來做波長分配與碼分配的最佳化且用於MAN(Metro Aera Network)，最後加入平型式之錯誤更正碼來增加與改善網路系統的效能。 (1) PON 智慧網路設計 (2) WDM-PON 與CDMA-PON 之智慧網路設計 (3) 平行架構之錯誤更正碼探討 (4) PON 智慧網路最佳化設計 (5) WDM-PON 與CDMA-PON 之網路協定設計 (6) 平行架構錯誤更正碼之硬體設計 (7) PON 智慧網路之控制器與基因演算法之實現 (8) WDM-PON 與CDMA-PON 網路最佳化設計 (9) 利用GA 來做波長與碼的分配最佳化 (10) 在MAN 中網路與WDM-PON/CDMA-PON 溝通之探討 (11) 智慧型網路結合平行架構之錯誤更正碼之分析[[sponsorship]]行政院國家科學委員

Design of Special Function Units in Modern Microprocessors

Today’s computing systems demand high performance for applications such as cloud computing, web-based search engines, network applications, and social media tasks. Such software applications involve an extensive use of hashing and arithmetic operations in their computation. In this thesis, we explore the use of new special function units (SFUs) for modern microprocessors, to accelerate such workloads. First, we design an SFU for hashing. Hashing can reduce the complexity of search and lookup from O(p) to O(p/n), where n bins are used and p items are being processed. In modern microprocessors, hashing is done in software. In our work, we propose a novel hardware hash unit design for use in modern microprocessors. Since the hash unit is designed at the hardware level, several advantages are obtained by our approach. First, a hardware-based hash unit executes a single hash instruction to perform a hash operation. In a software-based hashing in modern microprocessors, a hash operation is compiled into multiple instructions, thereby degrading performance. Second, software-based hashing stores hash data in a DRAM (also, hash operation entries can be stored in one of the cache levels). In a hardware-based hash unit, hash data is stored in a dedicated memory module (a hardware hash table), which improves performance. Third, today’s operating systems execute multiple applications (processes) in parallel, which entail high memory utilization. Hence the operating systems require many context switching between different processes, which results in many cache misses. In a hardware-based hash unit, the cache misses is reduced significantly using the dedicated memory module (hash table). These advantages all reduce the power consumption and increase the overall system performance significantly with a minimal increase in the microprocessor’s die area. We evaluate our hardware-based hash unit and compare its performance with software-based hashing. We start by evaluating our design approach at the micro-architecture level in terms of system performance. After that, we design our approach at the circuit level design to obtain the area overhead. Also, we analyze our design’s power and delay for each hash operation. These results are compared with a traditional hashing implementation. Then, we present an FPGA-based coprocessor for hash unit acceleration, applied to a virus checking application. Second, we present an SFU to speed up arithmetic operations. We call this arithmetic SFU a programmable arithmetic unit (PAU). In modern microprocessors, applications that require heavy arithmetic computations are done in software. To improve the performance for such computations, we present a programmable arithmetic unit (PAU), a partially reconfigurable methodology for arithmetic applications. The PAU consists of a set of IP blocks connected to a reconfigurable FPGA controller via a fast mesh-based interconnect. The IP blocks in the PAU can be any IP block such as adders, subtractors, multipliers, comparators and sign extension units. The PAU can have one or more copies of the same IP block (for example, 5 adders and 7 multipliers). The FPGA controller is an on-chip FPGA-based reconfigurable control fabric. The FPGA controller enables different arithmetic applications to be embedded on the PAU. The FPGA controller is programmed for different applications. The reconfigurable logic is based on a LUT-based design like a traditional FPGA. The FPGA controller and the IP blocks in the PAU communicate via a high speed ring data fabric. In our work, we use the PAU as an SFU in modern microprocessors. We compare the performance of different hardware-based arithmetic applications in the PAU with software-based implementations in modern microprocessors

The application of forward error correction techniques in wireless ATM

Bibliography: pages 116-121.The possibility of providing wireless access to an ATM network promises nomadic users a communication tool of unparalleled power and flexibility. Unfortunately, the physical realization of a wireless A TM system is fraught with technical difficulties, not the least of which is the problem of supporting a traditional ATM protocol over a non-benign wireless link. The objective of this thesis, titled "The Application of Forward Error Correction Techniques in Wireless ATM' is to examine the feasibility of using forward error correction techniques to improve the perceived channel characteristics to the extent that the channel becomes transparent to the higher layers and allows the use of an unmodified A TM protocol over the channel. In the course of the investigation that this dissertation describes, three possible error control strategies were suggested for implementation in a generic wireless channel. These schemes used a combination of forward error correction coding schemes, automatic repeat request schemes and interleavers to combat the impact of bit errors on the performance of the link. The following error control strategies were considered : 1. A stand alone fixed rate Reed-Solomon encoder/decoder with automatic repeat request. 2. A concatenated Reed-Solomon, convolution encoder/decoder with automatic request and convolution interleaving for the convolution codec. 3. A dynamic rate encoder/decoder using either a concatenated Reed-Solomon, convolution scheme or a Reed-Solomon only scheme with variable length Reed-Solomon words

THE APPLICATION OF REAL-TIME SOFTWARE IN THE IMPLEMENTATION OF LOW-COST SATELLITE RETURN LINKS

Digital Signal Processors (DSPs) have evolved to a level where it is feasible for digital modems with relatively low data rates to be implemented entirely with software algorithms. With current technology it is still necessary for analogue processing between the RF input and a low frequency IF but, as DSP technology advances, it will become possible to shift the interface between analogue and digital domains ever closer towards the RF input. The software radio concept is a long-term goal which aims to realise software-based digital modems which are completely flexible in terms of operating frequency, bandwidth, modulation format and source coding. The ideal software radio cannot be realised until DSP, Analogue to Digital (A/D) and Digital to Analogue (D/A) technology has advanced sufficiently. Until these advances have been made, it is often necessary to sacrifice optimum performance in order to achieve real-time operation. This Thesis investigates practical real-time algorithms for carrier frequency synchronisation, symbol timing synchronisation, modulation, demodulation and FEC. Included in this work are novel software-based transceivers for continuous-mode transmission, burst-mode transmission, frequency modulation, phase modulation and orthogonal frequency division multiplexing (OFDM). Ideal applications for this work combine the requirement for flexible baseband signal processing and a relatively low data rate. Suitable applications for this work were identified in low-cost satellite return links, and specifically in asymmetric satellite Internet delivery systems. These systems employ a high-speed (>>2Mbps) DVB channel from service provider to customer and a low-cost, low-speed (32-128 kbps) return channel. This Thesis also discusses asymmetric satellite Internet delivery systems, practical considerations for their implementation and the techniques that are required to map TCP/IP traffic to low-cost satellite return links

Current state of ASoC design methodology

This paper gives an overview of the current state of ASoC design methodology and presents preliminary results on evaluating the learning classifier system XCS for the control of a QuadCore. The ASoC design methodology can determine system reliability based on activity, power and temperature analysis, together with reliability block diagrams. The evaluation of the XCS shows that in the evaluated setup, XCS can find optimal operating points, even in changed environments or with changed reward functions. This even works, though limited, without the genetic algorithm the XCS uses internally. The results motivate us to continue the evaluation for more complex setups

Embedded CMOS Basecalling for Nanopore DNA Sequencing

DNA sequencing is undergoing a profound evolution into a mobile technology. Unfortunately the effort needed to process the data emerging from this new sequencing technology requires a compute power only available to traditional desktop or cloud-based machines. To empower the full potential of portable DNA solutions a means of efficiently carrying out their computing needs in an embedded format will certainly be required. This thesis presents the design of a custom fixed-point VLSI hardware implementation of an HMM-based multi-channel DNA sequence processor. A 4096 state (6-mer nanopore sensor) basecalling architecture is designed in a 32-nm CMOS technology with the ability to process 1 million DNA base pairs per second per channel. Over a 100 mm^2 silicon footprint the design could process the equivalent of one human genome every 30 seconds at a power consumption of around 5 W