The Bias Dependence of CMOS 1/F Noise Statistics, its Modeling and Impact on RF Circuits

In the last decade, wireless network routers, multi-media devices with Bluetooth© or similar communication capabilities, mobile cell-phones, and other “RF” devices have found widespread use in the consumer market. The integration and cost advantages of CMOS-only chips have attracted circuit designers in academia and industry, and CMOS technology is now a strong contender along with BiCMOS, and III-V semiconductors for analog / mixed signal and radio frequency applications. RF CMOS technology has numerous advantages that come with the feasibility of system-on-chip. These advantages include reduced fabrication cost and reduced pin count due to die sharing between analog and digital portions. Perhaps the most critical disadvantage of RF CMOS is the very high 1/f noise levels observed in MOSFETs in comparison to BJTs (bipolar-junction transistor). The silicon – silicondioxide interface is crucial to the operation of all MOSFETs, and unlike bipolar devices, MOSFETs are largely surface conductive devices, with device current flowing at or near the interface. This leads to the large 1/f noise associated with FETs. There has been on-going research to study the physical mechanism of 1/f noise. The compact models used to predict device noise in circuit simulations have also been improved. It has recently been observed that 1/f noise increases during the lifetime of a transistor. Also, large statistical variations in noise level have been reported. The existing models fail to explain such variability in 1/f noise. The work presented here extends the state-of-the art of 1/f noise modeling through experimental and theoretical analysis of noise reliability and statistics. A new model is developed based on a novel theory that investigates the relationship between the spatial profile of interface traps and the bias dependence of 1/f noise. The theory is tested against device noise measurements, as well as RF circuit phase noise measurements

Integrated Circuit Design for Hybrid Optoelectronic Interconnects

This dissertation focuses on high-speed circuit design for the integration of hybrid optoelectronic interconnects. It bridges the gap between electronic circuit design and optical device design by seamlessly incorporating the compact Verilog-A model for optical components into the SPICE-like simulation environment, such as the Cadence design tool. Optical components fabricated in the IME 130nm SOI CMOS process are characterized. Corresponding compact Verilog-A models for Mach-Zehnder modulator (MZM) device are developed. With this approach, electro-optical co-design and hybrid simulation are made possible. The developed optical models are used for analyzing the system-level specifications of an MZM based optoelectronic transceiver link. Link power budgets for NRZ, PAM-4 and PAM-8 signaling modulations are simulated at system-level. The optimal transmitter extinction ratio (ER) is derived based on the required receiver\u27s minimum optical modulation amplitude (OMA). A limiting receiver is fabricated in the IBM 130 nm CMOS process. By side- by-side wire-bonding to a commercial high-speed InGaAs/InP PIN photodiode, we demonstrate that the hybrid optoelectronic limiting receiver can achieve the bit error rate (BER) of 10-12 with a -6.7 dBm sensitivity at 4 Gb/s. A full-rate, 4-channel 29-1 length parallel PRBS is fabricated in the IBM 130 nm SiGe BiCMOS process. Together with a 10 GHz phase locked loop (PLL) designed from system architecture to transistor level design, the PRBS is demonstrated operating at more than 10 Gb/s. Lessons learned from high-speed PCB design, dealing with signal integrity issue regarding to the PCB transmission line are summarized

CMOS SPAD-based image sensor for single photon counting and time of flight imaging

The facility to capture the arrival of a single photon, is the fundamental limit to the detection of quantised electromagnetic radiation. An image sensor capable of capturing a picture with this ultimate optical and temporal precision is the pinnacle of photo-sensing. The creation of high spatial resolution, single photon sensitive, and time-resolved image sensors in complementary metal oxide semiconductor (CMOS) technology offers numerous benefits in a wide field of applications. These CMOS devices will be suitable to replace high sensitivity charge-coupled device (CCD) technology (electron-multiplied or electron bombarded) with significantly lower cost and comparable performance in low light or high speed scenarios. For example, with temporal resolution in the order of nano and picoseconds, detailed three-dimensional (3D) pictures can be formed by measuring the time of flight (TOF) of a light pulse. High frame rate imaging of single photons can yield new capabilities in super-resolution microscopy. Also, the imaging of quantum effects such as the entanglement of photons may be realised. The goal of this research project is the development of such an image sensor by exploiting single photon avalanche diodes (SPAD) in advanced imaging-specific 130nm front side illuminated (FSI) CMOS technology. SPADs have three key combined advantages over other imaging technologies: single photon sensitivity, picosecond temporal resolution and the facility to be integrated in standard CMOS technology. Analogue techniques are employed to create an efficient and compact imager that is scalable to mega-pixel arrays. A SPAD-based image sensor is described with 320 by 240 pixels at a pitch of 8μm and an optical efficiency or fill-factor of 26.8%. Each pixel comprises a SPAD with a hybrid analogue counting and memory circuit that makes novel use of a low-power charge transfer amplifier. Global shutter single photon counting images are captured. These exhibit photon shot noise limited statistics with unprecedented low input-referred noise at an equivalent of 0.06 electrons. The CMOS image sensor (CIS) trends of shrinking pixels, increasing array sizes, decreasing read noise, fast readout and oversampled image formation are projected towards the formation of binary single photon imagers or quanta image sensors (QIS). In a binary digital image capture mode, the image sensor offers a look-ahead to the properties and performance of future QISs with 20,000 binary frames per second readout with a bit error rate of 1.7 x 10-3. The bit density, or cumulative binary intensity, against exposure performance of this image sensor is in the shape of the famous Hurter and Driffield densitometry curves of photographic film. Oversampled time-gated binary image capture is demonstrated, capturing 3D TOF images with 3.8cm precision in a 60cm range

Analysis and design of a high power millimeter-wave power amplifier in a SiGe BiCMOS technology

Our current society is characterized by an ever increasing need for bandwidth leading towards the exploration of new parts of the electromagnetic spectrum for data transmission. This results in a rising interest and development of millimeter-wave (mm-wave) circuits which hold the promise of short range multi-gigabit wireless transmissions at 60GHz. These relatively new applications are to co-exist with more established mm-wave consumer products including satellite systems in the Ka-band (26.5GHz - 40GHz) allowing e.g.: video broadcasting, voice over IP (VoIP), internet acces to remote areas, ... Both need significant linear power amplification due to the high attenuation typical for this part of the spectrum, however, satellite systems demand a saturated output power which is easily an order of magnitude larger (output powers in excess of 30dBm / 1W). Monolithic microwave integrated circuits (MMICs) employing III-V chip technologies, e.g.: gallium arsenide (GaAs), gallium nitride (GaN), have historically been the preferred choice to implement efficient mm-wave power amplifiers (PA) with a high saturated output power (>30dBm). To further increase the commercial viability of consumer products in this market segment a low manufacturing cost for the power amplifier, together with the possible integration of additional functions, is highly desirable. These features are the strongpoint of silicon based chip technologies like CMOS and SiGe BiCMOS. However, these technologies have a breakdown voltage typically below 2V for nodes capable of millimeter-wave applications while III-V transistors with equivalent frequency performance demonstrate breakdown voltages in excess of 8V. Because of this, output powers of CMOS and SiGe BiCMOS Ka-band power amplifiers rarely exceed 20dBm which poses the main hurdle for using these technologies in satellite communication (SATCOM). To overcome the limited output power of a single amplifying cell in a silicon technology, caused by the low breakdown voltage, multiple power amplifiers cells need to have their output power effectively combined on-chip. This requires the on-chip integration of high-Q passives within a relative small area to realize both the impedance transformation, to create the optimal load impedance for the different amplifier cells, and implement an efficient on-chip power combination network. Compared to III-V technologies this is again a challenge due to the use of a silicon substrate which introduces higher losses. Once a large enough on-chip output power is created, the issue of launching this signal to the outside world remains. Moreover, due to the limited efficiency of mm-wave PAs, the generated on-chip heat will increase when larger output power are required. This means a chipto-board interface with a low thermal resistance and a low loss electrical connection needs to be devised. Proof of the viability of silicon as a serious candidate for the integration of medium and high power Ka-band amplifiers will only be delivered by long term research and the actual creation of such an amplifier. In this context, the initial goal for the presented work is proposed. This consists of the creation of a power amplifier with a saturated output power above 24dBm (preferably 27dBm), a gain larger than 20dB and an efficiency in excess of 10% (preferably 15%). These specifications where conceived with the precondition of using a 250nm SiGe BiCMOS technology (IHP’s SG25H3) with an fT of 110GHz and a collector to emitter breakdown voltage in open base conditions (BVCEO) of 2.3V. The use of this technology is a significant challenge due to the limited speed, rule of thumb is to have at least one fifth of the fT as the operating frequency, which reflects in the attainable power added efficiency (PAE). On the other hand, proving the possible implementation in this “older” technology shows great potential towards the future integration in a fast technology (e.g.: IHP’s SG13G2, ft =300GHz). Next to issues caused by limitations of the chip technology, the proposed specifications allows to identify generic difficulties with high power silicon PA design, e.g.: design of efficient on-chip power combiners, thermal management, single-ended to differential conversion, ... As this work is of an academic nature the intention of this design was to leave the beaten track and explore alternative topologies. This has led to the adoption of a driver stage using translinear loops for biasing and a transformer-type Wilkinson power combiner previously only used in cable television (CATV) applications. Although the power combiner showed 2dB more loss than expected due to higher than expected substrate losses, both topologies show promise for further integration. Furthermore, an in-depth analysis was performed on the output stage which uses positive feedback to increase its gain. The entire design consists of a four-way power combining class AB power amplifier together with test structures of which the performance was verified by means of probing. Due to the previously mentioned higher than expected loss in the on-chip power combiner, the total output power and power added efficiency (PAE) was 2dB lower than expected from simulations. The result is a saturated output power at 32GHz of 24.1dBm with a PAE of 7.2% and a small signal gain of 25dB. This demonstrates the capability of SiGe BiCMOS to implement PA’s for medium-power mm-wave applications. Moreover, to the best of the author’s knowledge, this PA achieves the second highest saturated output power when comparing SiGe BiCMOS PA’s with center frequency in or close to the Ka-band. The 1dB compression point of this amplifier lies at 22.7dBm which is close to saturated output power and results in a low spectral regrowth when compared to commercial GaAs PA’s (compared with 2MBaud 16QAM input signal at 10dB back-off). Many possible improvements to this design remain. The most important would be the re-design of the on-chip power combiner, possibly with a floating ground shield, to reduce the losses and increase the total output power and PAE. Also the porting of the design to a faster chip technology might result in a considerable increase of the output stage efficiency at the cost of needing to combine more amplifier cells. The transition to a faster chip technology would additionally allow to use this design for alternative mm-wave applications like automotive radar at 79GHz andWiGig at 60GHz

Photodetectors

In this book some recent advances in development of photodetectors and photodetection systems for specific applications are included. In the first section of the book nine different types of photodetectors and their characteristics are presented. Next, some theoretical aspects and simulations are discussed. The last eight chapters are devoted to the development of photodetection systems for imaging, particle size analysis, transfers of time, measurement of vibrations, magnetic field, polarization of light, and particle energy. The book is addressed to students, engineers, and researchers working in the field of photonics and advanced technologies

Parallel reconfigurable single photon avalanche diode array for optical communications

There is a pressing need to develop alternative communications links due to a number of physical phenomena, limiting the bandwidth and energy efficiency of wire-based systems or economic factors such as cost, material-supply reliability and environmental costs. Networks have moved to optical connections to reduce costs, energy use and to supply high data rates. A primary concern is that current optical-detection devices require high optical power to achieve fast data rates with high signal quality. The energy required therefore, quickly becomes a problem. In this thesis, advances in single-photon avalanche diodes (SPADs) are utilised to reduce the amount of light needed and to reduce the overall energy budget. Current high performance receivers often use exotic materials, many of which have severe environmental impact and have cost, supply and political restrictions. These present a problem when it comes to integration; hence silicon technology is used, allowing small, mass-producible, low power receivers. A reconfigurable SPAD-based integrating receiver in standard 130nm imaging CMOS is presented for links with a readout bandwidth of 100MHz. A maximum count rate of 58G photon/s is observed, with a dynamic range of ≈ 79dB, a sensitivity of ≈ −31.7dBm at 100MHz and a BER of ≈ 1x10−9. We investigate the properties of the receiver for optical communications in the visible spectrum, using its added functionality and reconfigurability to experimentally explore non-ideal influences. The all-digital 32x32 SPAD array, achieves a minimum dead time of 5.9ns, and a median dark count rate (DCR) of 2.5kHz per SPAD. High noise devices can be weighted or removed to optimise the SNR. The power requirements, transient response and received data are explored and limiting factors similar to those of photodiode receivers are observed. The thesis concludes that data can be captured well with such a device but more electrical energy is needed at the receiver due to its fundamental operation. Overall, optical power can be reduced, allowing significant savings in either transmitter power or the transmission length, along with the advantages of an integrated digital chip

Research and design of high-speed advanced analogue front-ends for fibre-optic transmission systems

In the last decade, we have witnessed the emergence of large, warehouse-scale data centres which have enabled new internet-based software applications such as cloud computing, search engines, social media, e-government etc. Such data centres consist of large collections of servers interconnected using short-reach (reach up to a few hundred meters) optical interconnect. Today, transceivers for these applications achieve up to 100Gb/s by multiplexing 10x 10Gb/s or 4x 25Gb/s channels. In the near future however, data centre operators have expressed a need for optical links which can support 400Gb/s up to 1Tb/s. The crucial challenge is to achieve this in the same footprint (same transceiver module) and with similar power consumption as today’s technology. Straightforward scaling of the currently used space or wavelength division multiplexing may be difficult to achieve: indeed a 1Tb/s transceiver would require integration of 40 VCSELs (vertical cavity surface emitting laser diode, widely used for short‐reach optical interconnect), 40 photodiodes and the electronics operating at 25Gb/s in the same module as today’s 100Gb/s transceiver. Pushing the bit rate on such links beyond today’s commercially available 100Gb/s/fibre will require new generations of VCSELs and their driver and receiver electronics. This work looks into a number of state‐of-the-art technologies and investigates their performance restraints and recommends different set of designs, specifically targeting multilevel modulation formats. Several methods to extend the bandwidth using deep submicron (65nm and 28nm) CMOS technology are explored in this work, while also maintaining a focus upon reducing power consumption and chip area. The techniques used were pre-emphasis in rising and falling edges of the signal and bandwidth extensions by inductive peaking and different local feedback techniques. These techniques have been applied to a transmitter and receiver developed for advanced modulation formats such as PAM-4 (4 level pulse amplitude modulation). Such modulation format can increase the throughput per individual channel, which helps to overcome the challenges mentioned above to realize 400Gb/s to 1Tb/s transceivers

Pixel design and characterization of high-performance tandem OLED microdisplays

Organic Light-Emitting Diode (OLED) microdisplays - miniature Electronic Displays comprising a sandwich of organic light emitting diode over a substrate containing CMOS circuits designed to function as an active matrix backplane – were first reported in the 1990s and, since then, have advanced to the mainstream. The smaller dimensions and higher performance of CMOS circuit elements compared to that of equivalent thin film transistors implemented in technologies for large OLED display panels offer a distinct advantage for ultra-miniature display screens. Conventional OLED has suffered from lifetime degradation at high brightness and high current density. Recently, tandem-structure OLED devices have been developed using charge generation layers to implement two or more OLED units in a single stack. They can achieve higher brightness at a given current density. The combination of emissive-nature, fast response, medium to high luminance, low power consumption and appropriate lifetime makes OLED a favoured candidate for near-to-eye systems. However, it is also challenging to evaluate the pixel level optical response of OLED microdisplays as the pixel pitch is extremely small and relative low light output per pixel. Advanced CMOS Single Photon Avalanche Diode (SPAD) technology is progressing rapidly and is being deployed in a wide range of applications. It is also suggested as a replacement for photomultiplier tube (PMT) for photonic experiments that require high sensitivity. CMOS SPAD is a potential tool for better and cheaper display optical characterizations. In order to incorporate the novel tandem structure OLED within the computer aided design (CAD) flow of microdisplays, we have developed an equivalent circuit model that accurately describes the tandem OLED electrical characteristics. Specifically, new analogue pulse width modulation (PWM) pixel circuit designs have been implemented and fabricated in small arrays for test and characterization purposes. We report on the design and characterization of these novel pixel drive circuits for OLED microdisplays. Our drive circuits are designed to allow a state-of-the-art sub-pixel pitch of around 5 μm and implemented in 130 nm CMOS. A performance comparison with a previous published analogue PWM pixel is reported. Moreover, we have employed CMOS SPAD sensors to perform detailed optical measurements on the OLED microdisplay pixels at very high sampling rate (50 kHz, 10 μs exposure), very low light level (2×10-4 cd/m2) and over a very wide dynamic range (83 dB) of luminance. This offers a clear demonstration of the potential of the CMOS SPAD technology to reveal hitherto obscure details of the optical characteristics of individual and groups of OLED pixels and thereby in display metrology in general. In summary, there are three key contributions to knowledge reported in this thesis. The first is a new equivalent circuit model specifically for tandem structure OLED. The model is verified to provide accurately illustrate the electrical response of the tandem OLED with different materials. The second is the novel analogue PWM pixel achieve a 5μm sub-pixel pitch with 2.4 % pixel-to-pixel variation. The third is the new application and successful characterization experiment of OLED microdisplay pixels with SPAD sensors. It revealed the OLED pixel overshoot behaviour with a QIS SPAD sensor