Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

Tunnel Field Effect Transistors:from Steep-Slope Electronic Switches to Energy Efficient Logic Applications

The aim of this work has been the investigation of homo-junction Tunnel Field Effect Transistors starting from a compact modelling perspective to its possible applications. Firstly a TCAD based simulation study is done to explain the main device characteristics. The main differences of a Tunnel FET with respect to a conventional MOSFET is pointed out and the differences have been explained. A compact DC/AC model has been developed which is capable of describing the I-V characteristics in all regimes of operation. The model takes in to account ambi-polarity, drain side breakdown and all tunneling related physics. A temperature dependence is also added to the model to study the temperature independent behavior of tunneling. The model was further implemented in a Verilog-A based circuit simulator. Following calibration to experimental results of Silicon and strained-Silicon TFETs, the model has been also used to benchmark against a standard CMOS node for digital and analog applications. The circuits built with Tunnel FETs showed interesting temperature behavior which was superior to the compared CMOS node. In the same work, we also explore and propose solutions for using TFETs for low power memory applications. Both volatile and non-volatile memory concepts are investigated and explored. The application of a Tunnel FET as a capacitor-less memory has been experimentally demonstrated for the first time. New device concepts have been proposed and process flows for the same are developed to realize them in the clean room in EPFL

Dispositifs innovants à pente sous le seuil abrupte (du TEFT au Z -FET)

Tunnel à effet de champ (TFET) et un nouveau composant MOS à rétroaction que nous avons nommé le Z2-FET.Le Z2-FET est envisagé pour la logique faible consommation et pour les applications mémoire compatibles avecles technologies CMOS avancées. Nous avons étudié de manière systématique des TFETs avec différents oxydesde grille, matériaux et structures de canal, fabriqués sur silicium sur isolant totalement déserté (FDSOI). Lesmesures de bruit à basse fréquence (LFN) sur TFETs montrent la prédominance d'un signal aléatoiretélégraphique (RTS), qui révèle sans ambiguïté le mécanisme d effet tunnel. Un modèle analytique combinantl effet tunnel et le transport dans le canal a été développé, montrant un bon accord entre les résultatsexpérimentaux et les simulations.Nous avons conçu et démontré un nouveau dispositif (Z2-FET, pour pente sous le seuil verticale et zéroionisation par impact), qui présente une commutation extrêmement abrupte (moins de 1 mV par décade decourant), avec un rapport ION / IOFF >109, un large effet de hystérésis et un potentiel de miniaturisation jusqu'à 20nm. La simulation TCAD a été utilisée pour confirmer que la commutation électrique du Z2-FET fonctionne parl'intermédiaire de rétroaction entre les flux des électrons et trous et leurs barrières d'injection respectives. LeZ2-FET est idéalement adapté pour des applications mémoire à un transistor. La mémoire DRAM basée sur leZ2-FET montre des performances très bonnes, avec des tensions d'alimentation jusqu'à 1,1 V, des temps derétention jusqu'à 5,5 s et des vitesses d'accès atteignant 1 ns. Une mémoire SRAM utilisant un seul Z -FET estégalement démontrée sans nécessité de rafraichissement de l information stockée.Notre travail sur le courant GIDL intervenant dans les MOSFETs de type FDSOI a été combiné avec leTFET afin de proposer une nouvelle structure de TFETs optimisés, basée sur l'amplification bipolaire du couranttunnel. Les simulations de nouveau dispostif à injection tunnel amélioré par effet bipolaire (BET-FET) montrentdes résultats prometteurs, avec des ION supérierus à 4mA/ m et des pentes sous le seuil SS inférieures à 60mV/dec sur plus de sept décades de courant, surpassant tous les TFETs silicium rapportés à ce jour.La thèse se conclut par les directions de recherche futures dans le domaine des dispositifs à pente sous leseuil abrupte.This thesis is dedicated to studying sharp switching devices, including the tunneling field-effect-transistor(TFET) and a new feedback device we have named the Z2-FET, for low power logic and memory applicationscompatible with modern silicon technology. We have extensively investigated TFETs with various gate oxides,channel materials and structures, fabricated on fully-depleted silicon-on-insulator (FD-SOI) substrates.Low-frequency noise (LFN) measurements were performed on TFETs, showing the dominance of randomtelegraphy signal (RTS) noise, which reveals the tunneling mechanism. An analytical TFET model combiningtunneling and channel transport has been developed, showing agreement with the experimental and simulationresults.We also conceived and demonstrated a new device named the Z2-FET (for zero subthreshold swing andzero impact ionization), which exhibits extremely sharp switching with subthreshold swing SS 4.10-3 A/ mand SS < 60 mV/dec over 7 decades of current, outperforming all silicon-compatible TFETs reported to date.The thesis concludes with future research directions in the sharp-switching device arena.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Sub-10nm Transistors for Low Power Computing: Tunnel FETs and Negative Capacitance FETs

One of the major roadblocks in the continued scaling of standard CMOS technology is its alarmingly high leakage power consumption. Although circuit and system level methods can be employed to reduce power, the fundamental limit in the overall energy efficiency of a system is still rooted in the MOSFET operating principle: an injection of thermally distributed carriers, which does not allow subthreshold swing (SS) lower than 60mV/dec at room temperature. Recently, a new class of steep-slope devices like Tunnel FETs (TFETs) and Negative-Capacitance FETs (NCFETs) have garnered intense interest due to their ability to surpass the 60mV/dec limit on SS at room temperature. The focus of this research is on the simulation and design of TFETs and NCFETs for ultra-low power logic and memory applications. Using full band quantum mechanical model within the Non-Equilibrium Greens Function (NEGF) formalism, source-underlapping has been proposed as an effective technique to lower the SS in GaSb-InAs TFETs. Band-tail states, associated with heavy source doping, are shown to significantly degrade the SS in TFETs from their ideal value. To solve this problem, undoped source GaSb-InAs TFET in an i-i-n configuration is proposed. A detailed circuit-to-system level evaluation is performed to investigate the circuit level metrics of the proposed devices. To demonstrate their potential in a memory application, a 4T gain cell (GC) is proposed, which utilizes the low-leakage and enhanced drain capacitance of TFETs to realize a robust and long retention time GC embedded-DRAMs. The device/circuit/system level evaluation of proposed TFETs demonstrates their potential for low power digital applications. The second part of the thesis focuses on the design space exploration of hysteresis-free Negative Capacitance FETs (NCFETs). A cross-architecture analysis using HfZrOx ferroelectric (FE-HZO) integrated on bulk MOSFET, fully-depleted SOI-FETs, and sub-10nm FinFETs shows that FDSOI and FinFET configurations greatly benefit the NCFET performance due to their undoped body and improved gate-control which enables better capacitance matching with the ferroelectric. A low voltage NC-FinFET operating down to 0.25V is predicted using ultra-thin 3nm FE-HZO. Next, we propose one-transistor ferroelectric NOR type (Fe-NOR) non-volatile memory based on HfZrOx ferroelectric FETs (FeFETs). The enhanced drain-channel coupling in ultrashort channel FeFETs is utilized to dynamically modulate memory window of storage cells thereby resulting in simple erase-, program-and read-operations. The simulation analysis predicts sub-1V program/erase voltages in the proposed Fe-NOR memory array and therefore presents a significantly lower power alternative to conventional FeRAM and NOR flash memories

Through Silicon Via Field-Effect Transistor with Hafnia-based Ferroelectrics and the Doping of Silicon by Gallium Implantation Utilizing a Focused Ion Beam System

3-dimensional integration has become a standard to further increase the transistor density and to enhance the integrated functionality in microchips. Integrated circuits are stacked on top of each other and copper-filled through-silicon VIAs (TSVs) are the industry-accepted choice for their vertical electrical connection. The aim of this work is to functionalize the TSVs by implementing vertical field-effect transistors inside the via holes. The front and back sides of 200 ... 300 µm thin silicon wafers were doped to create the source/drain regions of n- and p-FETs. The TSVFETs showed very stable saturation currents and on/off current ratios of about 10^6 (n-TSVFET) and 10^3 (p-TSVFET) for a gate voltage magnitude of 4V. The use of hafnium zirconium oxide on a thin SiO_2 interface layer as gate dielectric material in a p-TSVFET, enabled the implementation of a charge trapping memory inside the TSVs, showing a memory window of about 1V. This allows the non-volatile storage of the transistor on/off state. In addition, the demonstration of the use of gallium as the source/drain dopant in planar p-FET test structures (ion implanted from a focused ion beam tool) paves the way for maskless doping and for a process flow with a low thermal budget. It was shown, that ion implanted gallium can be activated and annealed at relatively low temperatures of 500 °C ... 700 °C.:Abstract / Kurzzusammenfassung Danksagung Index I List of Figures III List of Tables X List of Symbols XI List of Abbreviations XV 1 Introduction 1 2 Fundamentals 5 2.1 Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) 5 2.1.1 Historical Development - Technological Advancements 7 2.1.2 Field-Effect Transistors in Semiconductor Memories 10 2.2 3D Integration and the Use of TSVs (Through Silicon VIAs) 16 2.3 Doping of Silicon 19 2.3.1 Doping by Thermal Diffusion 20 2.3.2 Doping by Ion Implantation 22 3 Electrical Characterization 24 3.1 Resistivity Measurements 24 3.1.1 Resistance Determination by Four-Point Probes Measurement 24 3.1.2 Contact Resistivity 27 3.1.3 Doping Concentration 32 3.2 C-V Measurements 35 3.2.1 Fundamentals of MIS C-V Measurements 35 3.2.2 Interpretation of C-V Measurements 37 3.3 Transistor Measurements 41 3.3.1 Output Characteristics (I_D-V_D) 41 3.3.2 Transfer Characteristics (I_D-V_G) 42 4 TSV Transistor 45 4.1 Idea and Motivation 45 4.2 Design and Layout of the TSV Transistor 47 4.2.1 Design of the TSV Transistor Structures 47 4.2.2 Test Structures for Planar FETs 48 5 Variations in the Integration Scheme of the TSV Transistor 51 5.1 Doping by Diffusion from Thin Films 51 5.1.1 Determination of Doping Profiles 52 5.1.2 n- and p- TSVFETs Doped Manufactures by the Use of the Diffusion Technique 59 5.2 Ferroelectric Hafnium-Zirconium-Oxide (HZO) in the Gate Stack 81 5.2.1 Planar ferroelectric p-MOSFETs Doped by Thermal Diffusion 82 5.2.2 p-TSVFETs with Hafnium-Zirconium-Oxide Metal Gate 90 5.3 Doping by Ion Implantation of Gallium with a Focused Ion Beam (FIB) Tool 96 5.3.1 Ga doped Si Diodes 97 5.3.2 Planar p-MOSFETs Doped by Ga Implantation 108 5.3.3 Proposal for a parallel integration of Cu TSVs and p-TSVFETs 117 6 Summary and Outlook 120 Bibliography XVIII A Appendix XXXVI A.1 Resistivity and Dopant Density XXXVI A.2 Mask set for the TSVFET XXXVII A.3 Mask Design of the Planar Test Structures XXXVIII Curriculum Vitae XXXIX List of Scientific Publications XL

High-Density Solid-State Memory Devices and Technologies

This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms

Development of an Advanced Probe and Study of Edge Plasma Flows and Transport in Tokamaks

Energie is de levensadem van een moderne maatschappij. Ze is noodzakelijk om aan de menselijke behoeften, de toenemende levensverwachting en de stijgende levensstandaard te blijven voldoen. Thermonucleaire kernfusie is een (bijna) niet-vervuilende, veilige en zo goed als onuitputtelijke energievorm voor de toekomst. Fusie van lichte positief geladen deeltjes (kernen) gebeurt enkel bij extreem hoge temperaturen. De brandstof (het gas) is dan volledig geïoniseerd. We spreken dan van een plasma, ook wel de vierde aggregatietoestand genoemd. Het plasmavolume kan worden beperkt en opgesloten door middel van magnetische opsluiting zoals in een ‘tokamak’. Deze fusiemachine bestaat uit een torusvormige vacuümkamer waarin sterk magnetische velden het plasma opsluit en waarin temperaturen van meer dan 100 miljoen graden kunnen worden bereikt. Het experimentele werk, voorgesteld in dit doctoraatswerk, is uitgevoerd op twee tokamaks: TEXTOR (Jülich, Duitsland) en CASTOR (Praag, Tsjechië). Het onderzoek concentreert zich op de studie van randplasma’s met behulp van elektrische sondes. De belangrijke ongewenste energie- en deeltjesverliezen, die de opsluitingstijd van het hete centrumplasma beperken, staan centraal. Sondes lijden helaas onder aan de empirische ‘wet van diagnostieken’; het ‘gemak’ van interpretatie is omgekeerd evenredig met het gemak aan implementatie. De moeilijkheid bij de interpretatie van de gemeten plasmastromen ligt in het beschrijven ervan. Hoe precies stoort de sonde lokaal het plasma? Hoe zijn de lokale plasmaparameters gerelateerd tot het ongestoorde plasma veraf? Het eerste theoretische gedeelte van deze thesis neemt een ééndimensionaal quasi-neutraal vloeistofmodel onder de loep. Het sondemodel wordt verfijnd, gevalideerd, uitgebreid en het venster van toepasselijkheid wordt nauwkeurig gedefinieerd. In het tweede deel van dit doctoraatswerk staat een nieuwe geavanceerde sonde centraal. Deze gesofisticeerde sonde is ontworpen voor het gelijktijdig meten van allerlei randplasmaparameters in de TEXTOR tokamak. We tonen aan dat deze diagnostiek accuraat en betrouwbaar is. Het simultaan meten van al deze plasmaparameters en hun fluctuaties is een wereldwijd unicum. Het laatste deel kadert in de studie naar mechanismen die verantwoordelijk zijn voor de geobserveerde en ongewenste toename van deeltjestransport naar buiten toe tijdens instabiliteiten in randplasma’s. De experimentele resultaten zijn uitgevoerd op de tokamak CASTOR tijdens toegewijde experimenten van verbeterde plasmaopsluiting. Een belangrijke ontdekking is de geobserveerde dynamische koppeling tussen de parallelle plasmastroming en het radiale transport. Gelijkaardige fenomenen van niet-lineaire dynamische interacties tussen turbulent transport en parallelle stroming zijn gerapporteerd op de veel grotere tokamak JET onder compleet verschillende plasmacondities waarmee wordt gesuggereerd dat de achterliggende fysica van universele aard is. Er wordt bovendien aangetoond dat de fysica van stromingen in het randplasma nood heeft aan een driedimensionale beschrijving waarin de verscheidene componenten die het fenomeen voortbrengt dienen te worden beschouwd

금속산화물 기반 저항변화메모리 소자의 노이즈 특성과 그것의 응용에 관한 연구

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·컴퓨터공학부, 2023. 2. 김재준.In the current pyramid-like structures memory hierarchy, it consists of, from top to bottom, a processing core, cache memory by static random access memory (SRAM), main memory by dynamic random access memory (DRAM), and storage memory by solid-state disk (SSD), or hard disk drive (HDD). In general, the closer to the processing core, the more high-speed operation is required, whereas the farther away from the core, the higher storage capacity is demanded. Consequently, the performance gap between DRAM and NAND Flash memory, which are currently major memory technologies, is continuously increasing. However, the need for new memory technology is increasing in order to solve the problem of data processing speed due to the explosive increase in the amount of data and the physical limitation of the existing memory technologies that has been raised for a long time. In addition, research and development on the storage class memory (SCM) technology is in progress as method of implementing In-Memory Process, a concept to solve the problem of Von Neumann architecture in various research groups. Among the candidates on the SCM, which satisfies both the high speed of DRAM and the density of NAND Flash, the resistive switching random access memory (RRAM) has been widely investigated as a leading candidate for next generation nonvolatile memory applications due to RRAMs advantageous features such as simple structure, low cost, high density, fast operation, and CMOS compatibility. However, the reliability issues which PCM suffered from is also being reproduced in RRAM. RRAMs various issues such as endurance, retention, and uniformity stem from intrinsic variability because resistive switching mechanism of RRAM itself is fundamentally stochastic. The main content of this dissertation is to develop a new electrical analysis technique to improve the reliability of RRAM. First, the elementary low frequency noise (LFN) characteristics of various RRAM devices were analyzed, and the correlation between LFN characteristics and the conduction/resistive switching mechanisms was experimentally verified. Also, it was suggested that the LFN measurement can be an additional analysis technique for devices degradation mechanism and multi-level cell (MLC) operation. Finally, from the random telegraph noise (RTN) measurement, we conducted a study to extract the position and energy of traps that can cause cells failure. The experiment on the extraction of traps physical information using the RTN measurement was conducted for the first in this study, and then research findings provided researchers with guidelines for the RTN analysis of RRAM.현재의 메모리 계층도를 보면 CPU는 고속 동작을 요구하고, 외부메모리는 고용량을 필요로 하기 때문에, 현재의 주요 메모리 기술인 DRAM과 NAND Flash 메모리의 성능 격차는 지속적으로 늘어나고 있다. 하지만 데이터 양의 폭발적인 증가로 인한 데이터 처리 속도 문제, 그리고 오래전부터 제기 되어왔던 기존 메모리의 물리적 한계를 해결하기 위해서 새로운 메모리 기술에 대한 필요성이 증가하고 있다. 또한 기존 폰노이만방식의 컴퓨터 시스템 구조의 문제점을 해결하기 위한 방법인 In-Memory Process를 실현하기 위한 방법으로 DRAM의 high speed, 그리고 NAND Flash의 high density 모두를 만족하는 SCM (storage class memory)기술에 대한 관심이 증가하고 있다. SCM 후보군 중에서, 저항 변화 메모리 소자인 RRAM (Resistive Random Access Memory)은 MIM, cross-point 형태의 간단한 구조를 가지며, 공정 상 집적도 향상에 유리하고, 사용되는 물질이 CMOS공정과 호환 가능하다. 이러한 장점들로 인해 기존 Flash 메모리 소자의 대안으로 학계에서 많은 연구가 진행 되어 왔지만, 한 단계 앞서 연구가 진행되었던 PCM (Phase change RAM)이 겪고 있는 신뢰성 문제가 RRAM에서도 재현되고 있다. RRAM의 신뢰성 문제는 RRAM의 저항 스위칭 메커니즘 자체가 근본적으로 확률적이기 때문에 본질적 변동성에서 기인하는 것이다. 본 논문의 주요 내용은 RRAM의 신뢰성 향상을 위해서 새로운 전기적 분석기법을 개발하는 것이다. 우선 다양한 메커니즘으로 동작하는 RRAM소자의 기본적인 저주파 잡음 특성을 분석하고, 이를 소자의 전도 메커니즘 및 저항 변화 메커니즘과의 연관성을 검증하였다. 측정결과를 기존 저주파 잡음 이론을 통해 해석하고, 다양한 소자에 이를 적용시켜 저주파 잡음 분석 기법이 RRAM의 동작 메커니즘 분석에 이용할 수 있음을 증명하였다. 또한, 소자의 열화 메커니즘 및 MLC (Multi-Level Cell) 분석에 있어서도 저주파 잡음 측정이 추가적인 분석기법이될 수 있음을 제시하였다. 마지막으로, 소자의 저주파 잡음 특성 중 하나인 RTN (Random Telegraph Noise)특성 분석을 통해 셀의 fail 을 일으킬 수 있는 trap의 위치 및 에너지를 추출하는 연구를 진행하였다. RRAM의 trap정보 추출에 관한 측정 및 분석은 본 연구에서 최초로 진행되었던 것이고, 이후 RRAM의 RTN분석에 가이드라인을 제시하였다.Chapter1 Introduction 1 1.1 Memory trends 1 1.1.1 Memory wall 1 1.1.2 In-memory processing 3 1.2 SCM technologies 4 1.2.1 Phase change memory 4 1.2.2 Magnetic memory 6 1.2.3 Ferroelectric memory 7 1.2.4 Resistive memory 8 1.3 Thesis content overview 12 1.3.1 Thesis objectives 12 1.3.2 Thesis outline 13 Chapter2 Overview on conduction mechanisms 14 2.1 Electrode-limited conduction mechanisms 14 2.1.1 Schottky emission 15 2.1.2 Fowler-Nordheim (F-N) and direct tunneling 17 2.2 Bulk-limited conduction mechanisms 18 2.2.1 Poole-Frenkel (P-F) emission 18 2.2.2 Ohmic conduction 19 2.2.3 Space charge limited conduction (SCLC) 20 Chapter3 LFN applications for RRAM analysis 23 3.1 Introduction to 1/f 23 3.2 LFN application (1): Resistive switching analysis 26 3.3 LFN application (2): MLC analysis 30 3.4 LFN application (3): Degradation analysis 35 Chapter4 Analysis of conduction mechanism using LFN 39 4.1 Thermochemical mechanism RRAM 39 4.1.1 Fabrication 39 4.1.2 Experimental results: RS and I-V characteristics 40 4.1.3 Experimental results: LFN characteristics 46 4.2 Valence change mechanism RRAM 50 4.2.1 Fabrication 50 4.2.2 Experimental results: RS and I-V characteristics 52 4.2.3 Experimental results: LFN characteristics 55 4.3 Comparative analysis of conduction mechanism 58 4.3.1 Fabrication 58 4.3.2 Experimental results: RS and I-V characteristics 61 4.3.3 Experimental results: LFN characteristics 63 Chapter5 Random telegraph noise (RTN) in RRAM 67 5.1 Introduction to RTN 67 5.2 RTN in RRAM 69 5.2.1 Methodology for extracting trap information 69 5.2.2 Experimental results 73 Chapter6 78 Conclusions 78박

높은 구동 전류와 낮은 문턱전압 이하 스윙을 가지는 L자 형태의 터널링 전계효과 트랜지스터

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 2. 박병국.In order to solve power crisis in highly-scaled CMOS technology, a novel tunnel field-effect transistors (TFETs), named L-shaped TFETs, have been proposed and its electrical properties are examined. It features band-to-band tunneling (BTBT) direction parallel to the normal electric field induced by gate electrode. Because carrier injection is occurred perpendicular to the channel direction, cross-sectional area and barrier width of BTBT junction could be defined by structural parameters. Using the commercial TCAD device simulator, its electrical characteristics are examined and optimized. It is expected that the L-shaped TFETs will reveal better performance than conventional ones in terms of subthreshold swing (S), on-current (Ion) and short channel effect. In addition, the performance of L-shaped TFET inverters has been compared with that of conventional TFET ones for its complementary logic application. After the key process techniques are obtained, control and comparison samples are fabricated at Inter-University Semiconductor Research Center (ISRC) of Seoul National University (SNU), Korea. The main process technique is as follow: in-situ doped epitaxial layer growth for constantly doped source region, selective epitaxial layer growth of silicon at low temperature for tunneling region, and guarantee sub-3-nm gate dielectric. From the electrical measurement of transfer and output characteristics, it is verified that 102 mV/dec minimum S in conventional TFET is improve to 7, 34 and 59 mV/dec in L-shaped TFET. In addition, the Ion of L-shaped TFET is more than 10 times larger than that of conventional one. Extracting several parameters such as source/drain resistance, channel resistance, mobility, and tunneling resistance, it is clear that the improved performance comes from the reduction of tunneling resistance. From this study, it is demonstrated that L-shaped TFET will be one of the most promising candidate for a next-generation low-power device.Abstract i Contents iii List of Tables v List of Figures vi Chapter 1 Introduction 1 1.1 NECESSITY OF ALTERNATIVES TO CMOS 1 1.2 TUNNEL FIELD-EFFECT TRANSISTORS (TFETS) 4 1.3 TECHNICAL ISSUES OF TFETS 7 1.4 SCOPE OF THESIS 10 Chapter 2 L-shaped TFET 11 2.1 FEATURES OF L-SHAPED TFET 11 2.2 DESIGN OPTIMIZATION 17 2.3 CORNER EFFECT 27 2.4 FURTHER IMPROVEMENT AND CIRCUIT APPLICATION 36 2.5 SUMMARY OF TARGET DEVICE 40 Chapter 3 Device Fabrication 42 3.1 FABRICATION OF CONTROL TFETS 42 3.2 KEY PROCESS DESIGNS FOR L-SHAPED TFETS 45 3.3 FABRICATION OF L-SHAPED TFET 51 3.4 SIDEWALL SPACER FOR MINIMIZATION OF MIS-ALIGNMENT 56 Chapter 4 Device Characteristics 59 4.1 METAL-OXIDE-SEMICONDUCTOR (MOS) CAPACITOR 59 4.2 CONTROL SAMPLES OF CONVENTIONAL PLANAR TFETS 63 4.3 L-SHAPED TFETS 71 4.4 EXTRACTION OF SEVERAL ELECTRICAL PARAMETERS 76 Chapter 5 80 Conclusions 80 Bibliography 82 Abstract in Korean 89 Curriculum Vitae 91Docto

Gated-Diode Memory Cell and Array Utilizing GIDL Current

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 2. 이종호.In this dissertation, the gated-diode memory cell and array utilizing the gate-induced drain leakage (GIDL) current is proposed and investigated for ultra-high density memory device. In the gated-diode memory, there is no short-channel effect (SCE) which is the critical issue for scaling down of the cell in conventional FET type memories. In addition, the random access can be possible in array structure although the cells are connected serially like as conventional NAND flash memory array, because the n+ diffusion region is directly connected to all cells which are connected in a bit-line (BL). In the gated-diode memory, Fowler-Nordheim (FN) tunneling is used for injection of electrons and band-to-band-tunneling (BTBT) induced hot-hole injection is used for injection of holes. To sense the cell state, the GIDL current is detected with negative gate bias condition. The GIDL current is increased and decreased by the stored electrons and holes, respectively. Recent trend of nonvolatile memories are introduced in Chapter 1. In Chapter 2, Gated-diode memory utilizing the GIDL current is introduced. In Chapter 3, fabrication process and measured data of gated-diode memory cell and array utilizing GIDL current is presented. Three methods of fabrication process is represented and key process technologies are shown with SEM images. In Chapter 4, the comparison between measurement and simulation is done and improved device structure with SiGe material is investigated to increase the sensing current (GIDL current). In Appendix, the low-frequency noise (LFN) characteristics of GIDL current in MOSFETs are investigated.Abstract i Contents iii Chapter 1 Introduction………………………………………………1 1.1 Flash Memory Technology………………………………………1 1.2 Basic Operation of Flash Memory……………………………4 1.3 3D stacked NAND Flash Memory…………………………6 1.4 Emerging New Memory……………………………………9 Chapter 2 Gated-Diode Memory utilizing GIDL Current………10 2.1 Introduction of GIDL Current……………………………10 2.2 Introduction of Gated-Diode Memory……………15 Chapter 3 Fabrication and Electrical Characteristics of SONOS Gated-Diode Memory Cell and Array utilizing GIDL Current…………………………………………………21 3.1 Fabrication Process of Gated-diode Memory with Fin Structure ……………………………………………………………………21 3.2 SEM Images of Fabricated Structures and Key Process Issues …………………………………………………………………31 3.3 Electrical Characteristics of Fabricated SONOS Gated-Diode Memory Cell and Array utilizing GIDL Current……………36 Chapter 4 Optimization of Gated-Diode Memory……………43 4.1 Comparison between Measurement and Simulation………43 4.2 Increase of GIDL current using SiGe……… …………………47 Chapter 5 Conclusions……………………………………………55 Appendix Low Frequency Noise of GIDL Current in MOSFETs …………………………………………………………56 A.1 LFN of GIDL and Channel Currents…………………………56 A.2 LFN of GIDL Current in n- and p-type MOSFETs…………67 A.3 RTN in GIDL and Gate Edge Tunneling Currents…………72 A.4 Model for RTN in GIDL Current…………………………85 Bibliography……………………………………………90 Abstract in Korean………………………………………96Docto