FishMark: A Linked Data Application Benchmark

Abstract. FishBase is an important species data collection produced by the FishBase Information and Research Group Inc (FIN), a not-forprofit NGO with the aim of collecting comprehensive information (from the taxonomic to the ecological) about all the world’s finned fish species. FishBase is exposed as a MySQL backed website (supporting a range of canned, although complex queries) and serves over 33 million hits per month. FishDelish is a transformation of FishBase into LinkedData weighing in at 1.38 billion triples. We have ported a substantial number of FishBase SQL queries to FishDelish SPARQL query which form the basis of a new linked data application benchmark (using our derivative of the Berlin SPARQL Benchmark harness). We use this benchmarking framework to compare the performance of the native MySQL application, the Virtuoso RDF triple store, and the Quest OBDA system on a fishbase.org like application.

Peptide mass fingerprinting using field-programmable gate arrays

The reconfigurable computing paradigm, which exploits the flexibility and versatility of field-programmable gate arrays (FPGAs), has emerged as a powerful solution for speeding up time-critical algorithms. This paper describes a reconfigurable computing solution for processing raw mass spectrometric data generated by MALDI-TOF instruments. The hardware-implemented algorithms for denoising, baseline correction, peak identification, and deisotoping, running on a Xilinx Virtex-2 FPGA at 180 MHz, generate a mass fingerprint that is over 100 times faster than an equivalent algorithm written in C, running on a Dual 3-GHz Xeon server. The results obtained using the FPGA implementation are virtually identical to those generated by a commercial software package MassLynx

A Readout System for the STAR Time Projection Chamber

We describe the readout electronics for the STAR Time Projection Chamber. The system is made up of 136,608 channels of waveform digitizer, each sampling 512 time samples at 6-12 Mega-samples per second. The noise level is about 1000 electrons, and the dynamic range is 800:1, allowing for good energy loss ($dE/dx$) measurement for particles with energy losses up to 40 times minimum ionizing. The system is functioning well, with more than 99% of the channels working within specifications.Comment: 22 pages + 8 separate figures; 2 figures are .jpg photos to appear in Nuclear Instruments and Method

차세대 자동차용 카메라 데이터 통신을 위한 비대칭 동시 양방향 송수신기의 설계

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022.2. 정덕균.본 학위 논문에서는 차세대 자동차용 카메라 링크를 위해 높은 속도의 4레벨 펄스 진폭 변조 신호와 낮은 속도의 2레벨 펄스 진폭 변조 신호를 통신하는 비대칭 동시 양방향 송수신기의 설계 기술에 대해 제안하고 검증되었다. 첫번째 프로토타입 설계에서는, 10B6Q 직류 밸런스 코드를 탑재한 4레벨 펄스 진폭 변조 송신기와 고정된 데이터와 참조 레벨을 가지는 4레벨 펄스 진폭 변조 적응형 수신기에 대한 내용이 기술되었다. 4레벨 펄스 진폭 변조 송신기에서는 교류 연결 링크 시스템에 대응하기 위한 면적 및 전력 효율성이 좋은 10B6Q 코드가 제안되었다. 이 코드는 직류 밸런스를 맞추고 연속적으로 같은 심볼을 가지는 길이를 6개로 제한 시킨다. 비록 여기서는 입력 데이터 길이 10비트를 사용하였지만, 제안된 기술은 카메라의 다양한 데이터 타입에 대응할 수 있도록 입력 데이터 길이에 대한 확장성을 가진다. 반면, 4레벨 펄스 진폭 변조 적응형 수신기에서는, 샘플러의 옵셋을 최적으로 제거하여 더 낮은 비트에러율을 얻기 위해서, 기존의 데이터 및 참조 레벨을 조절하는 대신, 이 레벨들은 고정시키고 가변 게인 증폭기를 적응형으로 조절하도록 하였다. 상기 10B6Q 코드 및 고정 데이터 및 참조레벨 기술을 가진 프로토타입 칩들은 40 나노미터 상호보완형 메탈 산화 반도체 공정으로 제작되었고 칩 온 보드 형태로 평가되었다. 10B6Q 코드는 합성 게이트 숫자는 645개와 함께 단 0.0009 mm2 의 면적 만을 차지한다. 또한, 667 MHz 동작 주파수에서 단 0.23 mW 의 전력을 소모한다. 10B6Q 코드를 탑재한 송신기에서 8-Gb/s 4레벨 펄스 진폭 변조 신호를 고정 데이터 및 참조 레벨을 가지는 적응형 수신기로 12-m 케이블 (22-dB 채널 로스) 을 통해서 보낸 결과 최소 비트 에러율 108 을 달성하였고, 비트 에러율 105 에서는 아이 마진이 0.15 UI x 50 mV 보다 크게 측정되었다. 송수신기를 합친 전력 소모는 65.2 mW (PLL 제외) 이고, 성과의 대표수치는 0.37 pJ/b/dB 를 보여주었다. 첫번째 프로토타입 설계을 포함하여 개선된 두번째 프로토타입 설계에서는, 12-Gb/s 4레벨 펄스 진폭 변조 정방향 채널 신호와 125-Mb/s 2레벨 펄스 진폭 변조 역방향 채널 신호를 탑재한 비대칭 동시 양방향 송수신기에 대해 기술되고 검증되었다. 제안된 넓은 선형 범위를 가지는 하이브리드는 gmC 저대역 통과 필터와 에코 제거기와 함께 아웃바운드 신호를 24 dB 이상 효율적으로 감소시켰다. 또한, 넓은 선형 범위를 가지는 하이브리드와 함께 게인 감소기를 형성하게 되는 선형 범위 증폭기를 통해 4레벨 펄스 진폭 변조 신호의 선형성과 진폭의 트레이드 오프 관계를 깨는 것이 가능하였다. 동시 양방향 송수신기 칩은 40 나노미터 상호보완형 메탈 산화 반도체 공정으로 제작되었다. 상기 설계 기술들을 이용하여, 4레벨 펄스 진폭 변조 및 2레벨 펄스 진폭 변조 송수신기 모두 5m 채널 (채널 로스 15.9 dB) 에서 1E-12 보다 낮은 비트 에러율을 달성하였고, 총 78.4 mW 의 전력 소모를 기록하였다. 종합적인 송수신기는 성과 대표지표로 0.41 pJ/b/dB 와 함께 동시 양방향 통신 아래에서 4레벨 펄스 진폭 변조 신호 및 2레벨 펄스 진폭 변조 신호 각각에서 아이 마진 0.15 UI 와 0.57 UI 를 달성하였다. 이 수치는 성과 대표지표 0.5 이하를 가지는 기존 동시 양방향 송수신기와의 비교에서 최고의 아이 마진을 기록하였다.In this dissertation, design techniques of a highly asymmetric simultaneous bidirectional (SB) transceivers with high-speed PAM-4 and low-speed PAM-2 signals are proposed and demonstrated for the next-generation automotive camera link. In a first prototype design, a PAM-4 transmitter with 10B6Q DC balance code and a PAM-4 adaptive receiver with fixed data and threshold levels (dtLevs) are presented. In PAM-4 transmitter, an area- and power-efficient 10B6Q code for an AC coupled link system that guarantees DC balance and limited run length of six is proposed. Although the input data width of 10 bits is used here, the proposed scheme has an extensibility for the input data width to cover various data types of the camera. On the other hand, in the PAM-4 adaptive receiver, to optimally cancel the sampler offset for a lower BER, instead of adjusting dtLevs, the gain of a programmable gain amplifier is adjusted adaptively under fixed dtLevs. The prototype chips including above proposed 10B6Q code and fixed dtLevs are fabricated in 40-nm CMOS technology and tested in chip-on-board assembly. The 10B6Q code only occupies an active area of 0.0009 mm2 with a synthesized gate count of 645. It also consumes 0.23 mW at the operating clock frequency of 667 MHz. The transmitter with 10B6Q code delivers 8-Gb/s PAM-4 signal to the adaptive receiver using fixed dtLevs through a lossy 12-m cable (22-dB channel loss) with a BER of 1E-8, and the eye margin larger than 0.15 UI x 50 mV is measured for a BER of 1E-5. The proto-type chips consume 65.2 mW (excluding PLL), exhibiting an FoM of 0.37 pJ/b/dB. In a second prototype design advanced from the first prototypes, An asymmetric SB transceivers incorporating a 12-Gb/s PAM-4 forward channel and a 125-Mb/s PAM-2 back channel are presented and demonstrated. The proposed wide linear range (WLR) hybrid combined with a gmC low-pass filter and an echo canceller effectively suppresses the outbound signals by more than 24dB. In addition, linear range enhancer which forms a gain attenuator with WLR hybrid breaks the trade-off between the linearity and the amplitude of the PAM-4 signal. The SB transceiver chips are separately fabricated in 40-nm CMOS technology. Using above design techniques, both PAM-4 and PAM-2 SB transceivers achieve BER less than 1E-12 over a 5-m channel (15.9 dB channel loss), consuming 78.4 mW. The overall transceivers achieve an FoM of 0.41 pJ/b/dB and eye margin (at BER of 1E-12) of 0.15 UI and 0.57 UI for the forward PAM-4 and back PAM-2 signals, respectively, under SB communication. This is the best eye margin compared to the prior art SB transceivers with an FoM less than 0.5.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 DISSERTATION ORGANIZATION 4 CHAPTER 2 BACKGROUND ON AUTOMOTIVE CAMERA LINK 6 2.1 OVERVIEW 6 2.2 SYSTEM REQUIREMENTS 10 2.2.1 CHANNEL 10 2.2.2 POWER OVER DIFFERENTIAL LINE (PODL) 12 2.2.3 AC COUPLING AND DC BALANCE CODE 15 2.2.4 SIMULTANEOUS BIDIRECTIONAL COMMUNICATION 18 2.2.4.1 HYBRID 18 2.2.4.2 ECHO CANCELLER 20 2.2.5 ADAPTIVE RECEIVE EQUALIZATION 22 CHAPTER 3 AREA AND POWER EFFICIENT 10B6Q ENCODER FOR DC BALANCE 25 3.1 INTRODUCTION 25 3.2 PRIOR WORKS 28 3.3 PROPOSED AREA- AND POWER-EFFICIENT 10B6Q PAM-4 CODER 30 3.4 DESIGN OF THE 10B6Q CODE 33 3.4.1 PAM-4 DC BALANCE 35 3.4.2 PAM-4 TRANSITION DENSITY 35 3.4.3 10B6Q DECODER 37 3.5 IMPLEMENTATION AND MEASUREMENT RESULTS 40 CHAPTER 4 PAM-4 TRANSMITTER AND ADAPTIVE RECEIVER WITH FIXED DATA AND THRESHOLD LEVELS 45 4.1 INTRODUCTION 45 4.2 PRIOR WORKS 47 4.3 ARCHITECTURE AND IMPLEMENTATION 49 4.2.1 PAM-4 TRANSMITTER 49 4.2.2 PAM-4 ADAPTIVE RECEIVER 52 4.3 MEASUREMENT RESULTS 62 CHAPTER 5 ASYMMETRIC SIMULTANEOUS BIDIRECTIONAL TRANSCEIVERS USING WIDE LINEAR RANGE HYBRID 68 5.1 INTRODUCTION 68 5.2 PRIOR WORKS 70 5.3 WIDE LINEAR RANGE (WLR) HYBRID 75 5.3 IMPLEMENTATION 78 5.3.1 SERIALIZER (SER) DESIGN 78 5.3.2 DESERIALIZER (DES) DESIGN 79 5.4 HALF CIRCUIT ANALYSIS OF WLR HYBRID AND LRE 82 5.5 MEASUREMENT RESULTS 88 CHAPTER 6 CONCLUSION 97 BIBLIOGRAPHY 99 초 록 106박

Engineering evaluations and studies. Volume 3: Exhibit C

High rate multiplexes asymmetry and jitter, data-dependent amplitude variations, and transition density are discussed

SPS pilot signal design and power transponder analysis, volume 2, phase 3

The problem of pilot signal parameter optimization and the related problem of power transponder performance analysis for the Solar Power Satellite reference phase control system are addressed. Signal and interference models were established to enable specifications of the front end filters including both the notch filter and the antenna frequency response. A simulation program package was developed to be included in SOLARSIM to perform tradeoffs of system parameters based on minimizing the phase error for the pilot phase extraction. An analytical model that characterizes the overall power transponder operation was developed. From this model, the effects of different phase noise disturbance sources that contribute to phase variations at the output of the power transponders were studied and quantified. Results indicate that it is feasible to hold the antenna array phase error to less than one degree per power module for the type of disturbances modeled

Hardware simulation of Ku-band spacecraft receiver and bit synchronizer, volume 1

A hardware simulation which emulates an automatically acquiring transmit receive spread spectrum communication and tracking system and developed for use in future NASA programs involving digital communications is considered. The system architecture and tradeoff analysis that led to the selection of the system to be simulated is presented

Direct Antenna Modulation using Frequency Selective Surfaces

In the coming years, the number of connected wireless devices will increase dramatically, expanding the Internet of Things (IoT). It is likely that much of this capacity will come from network densification. However, base stations are inefficient and expensive, particularly the downlink transmitters. The main cause of this is the power amplifier (PA), which must amplify complex signals, so are expensive and often only 30% efficient. As such, the cost of densifying cellular networks is high. This thesis aims to overcome this problem through codesign of a low complexity, energy efficient transmitter through electromagnetic design; and a waveform which leverages the advantages and mitigates the disadvantages of the new technology, while being suitable for supporting IoT devices. Direct Antenna Modulation (DAM) is a low complexity transmitter architecture, where modulation occurs at the antenna at transmit power. This means a non-linear PA can efficiently amplify the carrier wave without added distortion. Frequency Selective Surfaces (FSS) are presented here as potential phase modulators for DAM transmitters. The theory of operation is discussed, and a prototype DAM for QPSK modulation is simulated, designed and tested. Next, the design process for a continuous phase modulating antenna is explored. Simulations and measurement are used to fully characterise a prototype, and it is implemented in a line-of-sight end-to-end communications system, demonstrating BPSK, QPSK and 8-PSK. Due to the favourable effects of spread spectrum signalling on FSS DAM performance, Cyclic Prefix Direct Sequence Spread Spectrum (CPDSSS) is developed. Conventional spreading techniques are extended using a cyclic prefix, making multipath interference entirely defined by the periodic autocorrelation of the sequence used. This is demonstrated analytically, through simulation and with experiments. Finally, CPDSSS is implemented using FSS DAM, demonstrating the potential of this new low cost, low complexity transmitter with CPDSSS as a scalable solution to IoT connectivity