Programmable latching probe microstructures for wafer testing applications

The objective of this thesis is to design a programmable wafer testing array on a single chip based on micro electromechanical systems (MEMS) and VLSI. The wafer-scale integration in this thesis is a programmable array of test probes that are used for engineering test of VLSI and ULSI silicon integrated circuits at the wafer level. This consists of two subsystems (1) the VLSI address circuits used for addressing and controlling the MEMS on the chip and (2) the latching probe MEMS microstructure array that actuates into position for testing VLSI wafers. Each of the subsystems have been designed, analyzed and simulated separately. These structures were then integrated into a demonstration 4x4 array forming a programmable probe card. A 3-micrometer critical dimension is used for both the VLSI CMOS and the MEMS physical design layouts. The fabrication technique for the MEMS microstructure is detailed. A standard 12-mask CMOS technology is used for the fabrication of the address circuits

Free spectral range electrical tuning of a high quality on-chip microcavity

Reconfigurable photonic circuits have applications ranging from next-generation computer architectures to quantum networks, coherent radar and optical metamaterials. However, complete reconfigurability is only currently practical on millimetre-scale device footprints. Here, we overcome this barrier by developing an on-chip high quality microcavity with resonances that can be electrically tuned across a full free spectral range (FSR). FSR tuning allows resonance with any source or emitter, or between any number of networked microcavities. We achieve it by integrating nanoelectronic actuation with strong optomechanical interactions that create a highly strain-dependent effective refractive index. This allows low voltages and sub-nanowatt power consumption. We demonstrate a basic reconfigurable photonic network, bringing the microcavity into resonance with an arbitrary mode of a microtoroidal optical cavity across a telecommunications fibre link. Our results have applications beyond photonic circuits, including widely tuneable integrated lasers, reconfigurable optical filters for telecommunications and astronomy, and on-chip sensor networks.Comment: Main text: 7 pages, 3 figures. Supplementary information: 7 pages, 9 figure

Concepts for 18/30 GHz satellite communication system, volume 1

Concepts for 18/30 GHz satellite communication systems are presented. Major terminal trunking as well as direct-to-user configurations were evaluated. Critical technologies in support of millimeter wave satellite communications were determined

The ALICE TPC, a large 3-dimensional tracking device with fast readout for ultra-high multiplicity events

The design, construction, and commissioning of the ALICE Time-Projection Chamber (TPC) is described. It is the main device for pattern recognition, tracking, and identification of charged particles in the ALICE experiment at the CERN LHC. The TPC is cylindrical in shape with a volume close to 90 m^3 and is operated in a 0.5 T solenoidal magnetic field parallel to its axis. In this paper we describe in detail the design considerations for this detector for operation in the extreme multiplicity environment of central Pb--Pb collisions at LHC energy. The implementation of the resulting requirements into hardware (field cage, read-out chambers, electronics), infrastructure (gas and cooling system, laser-calibration system), and software led to many technical innovations which are described along with a presentation of all the major components of the detector, as currently realized. We also report on the performance achieved after completion of the first round of stand-alone calibration runs and demonstrate results close to those specified in the TPC Technical Design Report.Comment: 55 pages, 82 figure

Design of Power/Analog/Digital Systems Through Mixed-Level Simulations

In recent years the development of the applications in the field of telecommunications, data processing, control, renewable energy generation, consumer and automotive electronics determined the need for increasingly complex systems, also in shorter time to meet the growing market demand. The increasing complexity is mainly due to the mixed nature of these systems that must be developed to accommodate the new functionalities and to satisfy the more stringent performance requirements of the emerging applications. This means a more complex design and verification process. The key to managing the increased design complexity is a structured and integrated design methodology which allows the sharing of different circuit implementations that can be at transistor level and/or at a higher level (i.e.HDL languages).In order to expedite the mixed systems design process it is necessary to provide: an integrated design methodology; a suitable supporting tool able to manage the entire design process and design complexity and its successive verification.It is essential that the different system blocks (power, analog, digital), described at different level of abstraction, can be co-simulated in the same design context. This capability is referred to as mixed-level simulation.One of the objectives of this research is to design a mixed system application referred to the control of a coupled step-up dc-dc converter. This latter consists of a power stage designed at transistor-level, also including accurate power device models, and the analog controller implemented using VerilogA modules. Digital controllers are becoming very attractive in dc-dc converters for their programmability, ability to implement sophisticated control schemes, and ease of integration with other digital systems. Thus, in this dissertation it will be presented a detailed design of a Flash Analog-to-Digital Converter (ADC). The designed ADC provides medium-high resolution associated to high-speed performance. This makes it useful not only for the control application aforementioned but also for applications with huge requirements in terms of speed and signal bandwidth. The entire design flow of the overall system has been conducted in the Cadence Design Environment that also provides the ability to mixed-level simulations. Furthermore, the technology process used for the ADC design is the IHP BiCMOS 0.25 µm by using 50 GHz NPN HBT devices

IC Ku-band Impatt Amplifier

High efficiency GaAs low-high-low IMPATTs were investigated. Theoretical analyses were employed to establish a design window for the material parameters to maximize microwave performance. Single mesa devices yielded typically 2 to 3 W with 16 to 23% efficiency in waveguide oscillator test circuits. IMPATTs with high reliability Pt/TiW/Pt/Au metallizations were subjected to temperature stress, non-rf bias-temperature stress, and rf bias-temperature stress. Assuming that temperature is the driving force behind the dominant failure mechanism, a mean-time-to-failure considerably greater than 500,000 hours is indicated by the stress tests. A 15 GHz, 4W, 56 dB gain microstrip amplifier was realized using GaAs FETs and IMPATTs. Power combining using a 3 db Lange coupler is employed in the power output stage having an intrinsic power-added efficiency of 15.7%. Overall dc-to-rf efficiency of the amplifier is 10.8%. The amplifier has greater than a 250 MHz, 1 db bandwidth; operates over the 0 deg to 50 C (base plate) temperature range with less than 0.5 db change in the power output; weighs 444 grams; and has a volume of 220 cu cm

A Low-Power Silicon-Photomultiplier Readout ASIC for the CALICE Analog Hadronic Calorimeter

The future e + e − collider experiments, such as the international linear collider, provide precise measurements of the heavy bosons and serve as excellent tests of the underlying fundamental physics. To reconstruct these bosons with an unprecedented resolution from their multi-jet final states, a detector system employing the particle flow approach has been proposed, requesting calorimeters with imaging capabilities. The analog hadron calorimeter based on the SiPM-on-tile technology is one of the highly granular candidates of the imaging calorimeters. To achieve the compactness, the silicon-photomultiplier (SiPM) readout electronics require a low-power monolithic solution. This thesis presents the design of such an application-specific integrated circuit (ASIC) for the charge and timing readout of the SiPMs. The ASIC provides precise charge measurement over a large dynamic range with auto-triggering and local zero-suppression functionalities. The charge and timing information are digitized using channel-wise analog-to-digital and time-to-digital converters, providing a fully integrated solution for the SiPM readout. Dedicated to the analog hadron calorimeter, the power-pulsing technique is applied to the full chip to meet the stringent power consumption requirement. This work also initializes the commissioning of the calorimeter layer with the use of the designed ASIC. An automatic calibration procedure has been developed to optimized the configuration settings for the chip. The new calorimeter base unit with the designed ASIC has been produced and its functionality has been tested