Calibration of DAC mismatch errors in sigma delta ADCs based on a sine-wave measurement

We present an offline calibration procedure to correct the nonlinearity due element mismatch in the digital-to-analog converter (DAC) of a multibit Sigma Delta-modulation A/D converter. The calibration uses a single measurement on a sinusoidal input signal, from which the DAC errors can be estimated. The main quality of the calibration method is that it can be implemented completely in the digital domain (or in software) and does not intervene in any way in the analog modulator circuit. This way, the technique is a powerful tool for verifying and debugging designs. Due to the simplicity of the method, it may be also a viable approach for factory calibration

A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology

This paper presents a CMOS 0.7-μm ΣΔ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16. It uses fully differential switched-capacitor circuits with a clock frequency of 35.2 MHz, and has a power consumption of 55 mW. Such a low oversampling ratio has been achieved through the combined usage of fourth-order filtering and multibit quantization. To guarantee stable operation for any input signal and/or initial condition, the fourth-order shaping function has been realized using a cascade architecture with three stages; the first stage is a second-order modulator, while the others are first-order modulators - referred to as a 2-1-1mb architecture. The quantizer of the last stage is 3 bits, while the other quantizers are single bit. The modulator architecture and coefficients have been optimized for reduced sensitivity to the errors in the 3-bit quantization process. Specifically, the 3-bit digital-to-analog converter tolerates 2.8% FS nonlinearity without significant degradation of the modulator performance. This makes the use of digital calibration unnecessary, which is a key point for reduced power consumption. We show that, for a given oversampling ratio and in the presence of 0.5% mismatch, the proposed modulator obtains a larger signal-to-noise-plus-distortion ratio than previous multibit cascade architectures. On the other hand, as compared to a 2-1-1single-bit modulator previously designed for a mixed-signal asymmetrical digital subscriber line modem in the same technology, the modulator in this paper obtains one more bit resolution, enhances the operating frequency by a factor of two, and reduces the power consumption by a factor of four.Comisión Interministerial de Ciencia y Tecnología TIC97-0580European Commission ESPRIT 879

Improved offline calibration for DAC mismatch in low OSR Sigma Delta ADCs with distributed feedback

We present an offline calibration method to correct the non-linearity due to DAC element mismatch in distributed feedback SigmaDelta-modulation A/D-converters. The improvement over previous methods is that not only the first feedback DAC is calibrated, but also the DACs that are coupled to later stages can be calibrated as well. This is needed in the case of Sigma Delta modulators with a low OSR, where the contribution of the second feedback DAC should not be neglected. The technique is based on a calibration measurement with a two-tone input signal

Multi-bit cascade ΣΔ modulator for high-speed A/D conversion with reduced sensitivity to DAC errors

This paper presents a ΣΔ modulator (ΣΔM) which combines single-bit and multi-bit quantization in a cascade architecture to obtain high resolution with low oversampling ratio. It is less sensitive to the non-linearity of the DAC than those previously reported, thus enabling the use of very simple analog circuitry with neither calibration nor trimming required.Comisión Interministerial de Ciencia y Tecnología TIC97-058

Double-Sampling Single-Loop EA Modulator Topologies for Broad-band Applications

This paper presents novel double sampling high-order single loop sigma-delta modulator structures for wide-band applications. To alleviate the quantization noise folding into the inband frequency region, two previously reported techniques are used. The digital-to-analog converter's sampling paths are implemented with the single-capacitor approach and an additional zero is placed at the half of the sampling frequency of the modulator's noise transfer function (NTF). The detrimental effect of this additional zero on both the NTF and signal transfer function is also resolved through the proposed modulator architectures with a low additional circuit requirement

Multi-bit cascade ΣΔ modulator for high-speed A/D conversion with reduced sensitivity to DAC errors

El pdf del artículo es la versión post-print.This paper presents a ΣΔ modulator (ΣΔM) which combines single-bit and multi-bit quantization in a cascade architecture to obtain high resolution with low oversampling ratio. It is less sensitive to the non-linearity of the DAC than those previously reported, thus enabling the use of very simple analog circuitry with neither calibration nor trimming required.This work has been supported by Spanish C.I.C.Y.T. under contract TIC97-0580.Peer reviewe

A hardware efficient 3-bit second-order dynamic element matching circuit clocked at 300MHz

International audienceA robust and hardware efficient dynamic element matching (DEM) algorithm is developed and used to design a 4th-order bandpass (BP) mismatch-shaping circuit, moved inside the feedback loop of a 6th-order bandpass continuous-time delta-sigma modulator. This algorithm is based on a shortened tree-structured scheme (STDEM) which can assure a stable high order mismatch-shaping with a modest circuit volume. The modulator has a 3-bit quantizer and 8 thermometric feedback DAC's cells. The designed DEM's circuits is simulated in 0.35μ- CMOS which can be clocked up to 300-MHz. The mismatch error floor is decreased of about 35dB in the band of interest. Its related circuit occupies of about 0.22mm2 area

Highly Linear 2,5-V CMOS ΣΔ Modulator for ADSL+

We present a 90-dB spurious-free dynamic range sigma–delta modulator (ΣΔM) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25μm CMOS process with metal–insulator–metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within +/-0.85 and +/-0.80 LSB, respectively. The ΣΔ modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the ΣΔ modulator.This work was supported by the European Union under IST Project 29261/MIXMODEST and IST Project 2001-34283/TAMES-2 and the Spanish MCyT and the ERDF under Project TIC2001-0929/ADAVERE.This work was supported by the European Union under IST Project 29261/MIXMODEST and IST Project 2001-34283/TAMES-2 and the Spanish MCyT and the ERDF under Project TIC2001-0929/ADAVERE.Peer reviewe

A rigorous approach to the robust design of continuous-time ΣΔ modulators

In this paper we present a framework for robust design of continuous-time Sigma Delta modulators. The approach allows to find a modulator which maintains its performance ( stability, guaranteed peak SNR, ...) over all the foreseen parasitic effects, provided it exists. For this purpose, we have introduced the S-figure as a criterion for the robustness of a continuous-time Sigma Delta modulator. This figure, inspired by the worst-case-distance methodology, indicates how close a design is to violating one of its performance requirements. Optimal robustness is obtained by optimizing this S-figure. The approach is illustrated through various design examples and is able to find modulators that are robust to excess loop delay, clock jitter and coefficient variations. As an application of the approach, we have quantified the effect of coefficient trimming. Even with poor trim resolution, good performance can be achieved provided beneficial initial system parameters are chosen. Another example illustrates the fact that also the out-of-band peaking behavior of the signal transfer function can be controlled with our design framework