Integrated circuits for efficient power delivery using pulse-width-modulation

Circuits and architectures for efficient power delivery have become crucial in emerging smart systems. Switching power amplifiers (PA) are very attractive for such applications, because they exhibit better efficiency compared to linear PA designs, due to saturated operation. Switching PAs also allow for utilization of deep submicron CMOS technologies, due to which these designs can be easily integrated with digital circuits, and can benefit from process scaling, in performance as well as in area. Pulse-width-modulation (PWM) is commonly used with switching PAs. A PWM signal typically employs a high-frequency switching pulse waveform as a carrier signal, wherein the pulse-width or duty-cycle of each pulse is modulated by a given low-frequency input signal. The carrier frequency can vary from several kHz to GHz, and is typically determined by the target application. In this thesis, efficient power-delivery circuits that use PWM with switching class-D stages are presented. Advanced circuit techniques, as well as architectures for PWM are proposed to enhance efficiency and circumvent the limitations of conventional architectures. A digitally-intensive transmitter using RF-PWM with a class-D PA is described in the first part of the thesis. The use of carrier switching for alleviating the dynamic range limitation that can be observed in classical RF-PWM implementations is introduced. The approach employs the full carrier frequency for half of the amplitude range, and the second harmonic of half of the carrier frequency, for the remainder of the amplitude range. This concept not only allows the transmitter to drive modulated signals with large peak-to-average power ratio (PAPR), but also improves the back-off efficiency due to reduced switching losses in the half carrier-frequency mode. A glitch-free phase selector is proposed that removes the deleterious glitches that can occur at the input data transitions. The phase-selector also prevents D flip-flop setup-and-hold time violations. The transmitter has been implemented in a 130-nm CMOS process. The measured peak output power and power-added-efficiency (PAE) are 25.6 dBm and 34%, respectively. While driving 802.11g 20-MHz 64-QAM OFDM signals, the average measured output power is 18.3 dBm and the PAE is 16%, with an EVM of -25.5 dB. The second part of the thesis describes a high-speed driver that provides a PWM output using a class-D PA. A PLL-based architecture is employed which eliminates the requirement for a precise ramp or triangular signal generator, and a high-speed comparator, which are typically used for PWM generation. Multi-level signaling is proposed to enhance back-off as well as peak efficiency, which is critical for signals with high PAPR. A differential, folded PWM scheme is introduced to achieve highly linear operation. 3-level operation is achieved without the requirement for additional supply source or sink paths, while 5-level operation is achieved with additional supply source and sink paths, compared to 2-level operation. The PWM driver has been implemented in a 130-nm CMOS process and can operate with a switching frequency of 40-to-170 MHz. For 2/3/5-level PA operation, with a 500 kHz sinusoidal input and 60 MHz switching frequency, the measured THD is -61/-62/-53 dB and corresponding efficiency is 71/83/86% with 175/200/220 mW output power level, respectively. Performance has also been verified for 2/3-level PA operation with a high PAPR signal with 500 kHz bandwidth. While intended as a general purpose amplifier, the approach is well-suited for applications such as power-line communications (PLC). The final part of the thesis introduces an efficient buck/buck-boost reconfigurable LED driver that supports PWM and PFM operation. The driver is based on peak current control. Rectified sin as well as sin² functions are employed in the reference signal to improve the power factor (PF) and total harmonic distortion (THD) of the buck and buck-boost converters. The design ensures that the peak of the inductor current maintains a constant level that is invariant for different AC line voltages. The operating mode of the design can be changed between PWM and PFM. The LED driver has been implemented in a 130-nm CMOS process. PF and THD are improved when the proposed reference is employed, and peak PF and lowest THD are 0.995/0.983/0.996 and 7.8/6.2/3.5% for the buck (PWM), buck (PFM), buck-boost (PFM) cases, respectively. The corresponding peak efficiency for the three cases is 88/92/91%, respectively.Electrical and Computer Engineerin

PLL-based digitally-intensive wireless transmitter architectures employing RF Pulse-Width Modulation

3G and 4G wireless networks have been recently proposed for Machine to Machine (M2M) communications in order to achieve ubiquitous coverage, robust security and high reliability. The most critical design consideration in transceivers for several portable Internet of Things (IoT) wireless communication applications is often power efficiency. This poses a key design challenge in wireless transmitters for communication standards that utilize high peak-to average power ratio (PAPR) signals. In this work, two PLL-based digitally-intensive wireless transmitter architectures employing RF-Pulse Width Modulation (RF-PWM) are presented, in order to address the efficiency challenge. The first architecture employs envelope and phase information, while the second utilizes quadrature I-Q signal components directly. A key contribution of this work is the use of analog-domain Pulse-Width Modulation (PWM) that can directly generate the output signals at the desired RF band without the need for frequency up-conversion and without degradation caused by quantization. By employing Class-D output stages, the proposed architectures can provide enhanced efficiency and allow for the use of broadband loads. These approaches make the designs suitable for multi-band and multi-mode operation. Furthermore, the digitally-intensive architectures can benefit from technology scaling. A prototype RF-PWM transmitter with a Class-D power amplifier (PA) which utilizes a polar approach is implemented in a 65-nm CMOS technology. For an LTE signal with a 1.4 MHz bandwidth and a 6.4 dB peak-to-average- power ratio (PAPR), the RF-PWM transmitter achieves a power-added efficiency (PAE) of 17.5% and an adjacent channel leakage ratio (ACLR) of -30.9 dBc and -31.1 dBc at an average output power of 16.1 dBm. The proposed transmitter achieves a peak output power of 22.4 dBm with 46.6% PAE and 38.8% efficiency for the full RF-PWM transmitter, including PAs.Electrical and Computer Engineerin

Techniques for Wideband All Digital Polar Transmission

abstract: Modern Communication systems are progressively moving towards all-digital transmitters (ADTs) due to their high efficiency and potentially large frequency range. While significant work has been done on individual blocks within the ADT, there are few to no full systems designs at this point in time. The goal of this work is to provide a set of multiple novel block architectures which will allow for greater cohesion between the various ADT blocks. Furthermore, the design of these architectures are expected to focus on the practicalities of system design, such as regulatory compliance, which here to date has largely been neglected by the academic community. Amongst these techniques are a novel upconverted phase modulation, polyphase harmonic cancellation, and process voltage and temperature (PVT) invariant Delta Sigma phase interpolation. It will be shown in this work that the implementation of the aforementioned architectures allows ADTs to be designed with state of the art size, power, and accuracy levels, all while maintaining PVT insensitivity. Due to the significant performance enhancement over previously published works, this work presents the first feasible ADT architecture suitable for widespread commercial deployment.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Circuits and architectures for broadband spectrum channelizers with sub-band gain control

Broadband receiver architectures for full-band or concurrent multi-band reception of signals are required in several applications. One approach to implementing such receivers is a spectrum channelizer that employs a frequency-folded analog-to-digital converter (FF-ADC). The design downconverts and channelizes a broadband input signal into multiple sub-bands at baseband by employing the harmonics of non-overlapping rectangular clocks. The downconverted and aliased baseband signal in each path is digitized by a baseband ADC, referred to as a sub-ADC below, that operates with a sampling rate that is lower than the Nyquist sampling rate set by the full bandwidth of the input signal. Sub-band separation is performed through digital harmonic rejection (HR) and image rejection (IR). The design operates similar to a time-interleaved ADC, except that it significantly reduces the bandwidth requirement of the samplers. If rectangular pulse waveforms are used in the FF-ADC down-converter, all sub-bands experience nearly equal gain during frequency down-conversion. Since all sub-bands are aliased to baseband before they are separated in the digital domain, a sub-band with large relative power can reduce the sub-ADC dynamic range that is available for other sub-bands, in addition to appearing as a blocker for other sub-bands. The research presented in this dissertation addresses approaches to overcome this issue, by embedding sub-band gain control within an FF-ADC. Chapter 2 proposes an approach that employs pulse-width-modulated local oscillator (PWM-LO) waveforms in the polyphase paths of an FF-ADC for scaling individual sub-band signal levels at baseband before digitization. The PWM-LO waveforms, which directly drive switches in each path, can be used to vary the gain in each sub-band by varying the level of harmonics in the waveforms. This is achieved by controlling the pulse-widths of the PWM-LO waveforms. This design avoids the requirement for N ×N switch matrices and variable transconductance cells in prior demonstrated approaches. The proposed architecture makes it possible to vary the spectral response of the FF-ADC with low signal-path complexity. Prediction of pulse widths for the desired harmonic, and hence the gain profile across all sub-bands, is performed using an off-chip supervised learning approach employing a neural network. Chapter 3 presents the implementation of a spectrum channelizer employing the PWM-LO-based sub-band amplitude control. The design allows for scaling the relative gain of the sub-bands over a 20-dB range. This relaxes the compression performance of the channelizer baseband and the sub-ADC dynamic range in the presence of sub-bands with significantly higher signal levels. Gain control on individual sub-bands is performed by employing customized PWM-LO waveforms,where the PWM-LO pulses are generated using delay-locked loops (DLLs). The off-chip neural-network based learning technique for estimating the PWM symbol pulse widths required for setting the desired LO harmonic levels is described. A 1.6 GS/s spectrum channelizer IC is implemented in a 65-nm CMOS process to verify the architecture. The measured channelizer gain is 51.6-56.5 dB without gain scaling and provides a range of 37-59 dB with PWM-LO gain control. Gain-scaling at a specific harmonic improves blocker compression in an unattenuated sub-band from -34 dBm to -16 dBm. The in-band gain compression with gain-scaling also increases from -32 dBm to -17 dBm. Chapter 4 describes a spectrum channelizer that uses voltage-mode downconversion. The approach requires a single voltage-mode input amplifier to drive the downconversion switches. Frequency-folding and sub-band gain control are achieved in a single signal path. This contrasts with the current-mode approach that requires a main FF-ADC path and a separate auxiliary path for sub-band gain control. By avoiding the requirement for an auxiliary input path, the approach presented here significantly simplifies the signal chain with identical gain-scaling capability. The contributions of this research and scope for future related work are summarized in Chapter 5.Electrical and Computer Engineerin

Baseband analog circuits in deep-submicron cmos technologies targeted for mobile multimedia

Three main analog circuit building blocks that are important for a mixed-signal system are investigated in this work. New building blocks with emphasis on power efficiency and compatibility with deep-submicron technology are proposed and experimental results from prototype integrated circuits are presented. Firstly, a 1.1GHz, 5th order, active-LC, Butterworth wideband equalizer that controls inter-symbol interference and provides anti-alias filtering for the subsequent analog to digital converter is presented. The equalizer design is based on a new series LC resonator biquad whose power efficiency is analytically shown to be better than a conventional Gm-C biquad. A prototype equalizer is fabricated in a standard 0.18μm CMOS technology. It is experimentally verified to achieve an equalization gain programmable over a 0-23dB range, 47dB SNR and -48dB IM3 while consuming 72mW of power. This corresponds to more than 7 times improvement in power efficiency over conventional Gm-C equalizers. Secondly, a load capacitance aware compensation for 3-stage amplifiers is presented. A class-AB 16W headphone driver designed using this scheme in 130nm technology is experimentally shown to handle 1pF to 22nF capacitive load while consuming as low as 1.2mW of quiescent power. It can deliver a maximum RMS power of 20mW to the load with -84.8dB THD and 92dB peak SNR, and it occupies a small area of 0.1mm2. The power consumption is reduced by about 10 times compared to drivers that can support such a wide range of capacitive loads. Thirdly, a novel approach to design of ADC in deep-submicron technology is described. The presented technique enables the usage of time-to-digital converter (TDC) in a delta-sigma modulator in a manner that takes advantage of its high timing precision while noise-shaping the error due to its limited time resolution. A prototype ADC designed based on this deep-submicron technology friendly architecture was fabricated in a 65nm digital CMOS technology. The ADC is experimentally shown to achieve 68dB dynamic range in 20MHz signal bandwidth while consuming 10.5mW of power. It is projected to reduce power and improve speed with technology scaling

A 2.4 GHz Phase Modulator for a WLAN OFDM Polar Transmitter in 0.18 um CMOS

This research focuses on the design and implementation of a digital active phase modulator path of a polar transmitter in the case of orthogonal frequency division multiplex WLAN application. The phase modulation path of the polar transmitter provides a constant envelope phase modulated signal to the Power amplifier(PA) , operating in nonlinear high efficient switching mode. The core design of the phase modulator is based on linear vector-sum phase shifting topology to differential quadrature input signals. The active phase shifter consists of a DAC that generates binary weighted currents for I and Q branches and differential signed adder that vector-sums the generated quadrature currents to generate the phase at the output.6 bits control the phase shifter, creating 64 states with the resolution of 5:625° for the whole 360°. The linear (binary weighted) vector-sum technique generates a reduction in the resultant amplitude that should be taken into consideration in case of nonlinear PA in polar transmission. On the other hand, the digital phase information is applied as the control bits to the phase shifter that determine the weightings and the signs of the I and Q vectors. The key point is the operation of the phase modulator in terms of phase accuracy, with the wideband modulation standard such as OFDM WLAN. A technique has been proposed to enable the polar phase modulator to operate with a real-time wideband data and to compensate for the phase shifter output reduction. Since the reduction in gain is due to vector sum resultant of I and Q currents, it is compensated by modifying the I and Q currents for each 64 phase states. The design is implemented using 0.18 um CMOS technology and measured with maximum data rate of 64 QAM,OFDM modulation of WLAN standard. The output amplitude of the phase shifter with the correction technique is approximately constant over the 64 states with maximum variation of 3.5mv from the constant peak to peak value. The maximum achieved phase error is about 2° with a maximum DNL of 0.257

Voltage and Time-Domain Analog Circuit Techniques for Scaled CMOS Technologies

CMOS technology scaling has resulted in reduced supply voltage and intrinsic voltage gain of the transistor. This presents challenges to the analog circuit designers due to lower signal swing and achievable signal to noise ratio (SNR), leading to increased power consumption. At the same time, device speed has increased in lower design nodes, which has not been directly beneficial for analog circuit design. This thesis presents voltage-domain and time-domain circuit scaling friendly circuit architectures that minimize the power consumption and benefit from the increasing transistor speeds. In the voltage-domain, an on-the-fly gain selection block is demonstrated as an alternative to the traditional MDAC architecture to enhance the input dynamic range of a medium-resolution medium-speed analog-to-digital converter (ADC) at reduced supply voltages. The proposed design also eliminates the need for a reference buffer, thus providing power savings. The measured prototype enhances the input dynamic range of a 12bit, 40MSPS ADC to 80.6dB at 1.2V supply voltage. In the time-domain, a generic circuit design approach is presented, followed by an in-depth analysis of Voltage-Controlled-Oscillator based Operational Transconductance Amplifiers (VCO-OTAs). A discrete-time-domain small-signal model based on the zero crossings of the internal VCOs is developed to predict the stability, the step response, and the frequency response of the circuit when placed in feedback. The model accurately predicts the circuit behavior for an arbitrary input frequency, even as the VCO free-running frequency approaches the unity-gain bandwidth of the closed-loop system, where other intuitive small-signal models available in the literature fail. Next, we present an application of VCO-OTA in designing a baseband trans-impedance amplifier (TIA) for current-mode receivers as a scaling-friendly and power-efficient alternative to the inverter-based OTA. We illustrate a design methodology for the choice of the VCO-OTA parameters in the context of a receiver design with an example of a 20MHz RF-channel-bandwidth receiver operating at 2GHz. Receiver simulation results demonstrate an improvement of up to 12dB in blocker 1dB compression point (B1dB) for slightly higher power consumption or up to 2.6x power reduction of the TIA resulting in up to 2x power reduction of the receiver for similar B1dB performance. Next, we present some examples of VCO-OTAs. We first illustrate the benefit of a VCO-OTA in a low-dropout-voltage regulator to achieve a dropout voltage of only100mV and operating down to 0.8V input supply, compared to the prototype based on traditional OTA with a minimum dropout voltage of 150mV, operating at a minimum of 1.2V supply. Both the capacitor-less prototypes can drive up to 1nF load capacitor and provide a current of 60mA. The next prototype showcases a method to reduce the power consumption of a VCO-OTA and spurs at the VCO frequency, with an application in the design of a fourth-order Butterworth filter at 4MHz. The thesis concludes with a design example of 0.2V VCO-OTA

Highly efficient linear CMOS power amplifiers for wireless communications

The rapidly expanding wireless market requires low cost, high integration and high performance of wireless communication systems. CMOS technology provides benefits of cost effectiveness and higher levels of integration. However, the design of highly efficient linear CMOS power amplifier that meets the requirement of advanced communication standards is a challenging task because of the inherent difficulties in CMOS technology. The objective of this research is to realize PAs for wireless communication systems that overcoming the drawbacks of CMOS process, and to develop design approaches that satisfying the demands of the industry. In this dissertation, a cascode bias technique is proposed for improving linearity and reliability of the multi-stage cascode CMOS PA. In addition, to achieve load variation immunity characteristic and to enhance matching and stability, a fully-integrated balanced PA is implemented in a 0.18-m CMOS process. A triple-mode balanced PA using switched quadrature coupler is also proposed, and this work saved a large amount of quiescent current and further improved the efficiency in the back-off power. For the low losses and a high quality factor of passive output combining, a transformer-based quadrature coupler was implemented using integrated passive device (IPD) process. Various practical approaches for linear CMOS PA are suggested with the verified results, and they demonstrate the potential PA design approach for WCDMA applications using a standard CMOS technology.PhDCommittee Chair: Kenney, J. Stevenson; Committee Member: Jongman Kim; Committee Member: Kohl, Paul A.; Committee Member: Kornegay, Kevin T.; Committee Member: Lee, Chang-H

Modulation Techniques for Biomedical Implanted Devices and Their Challenges

Implanted medical devices are very important electronic devices because of their usefulness in monitoring and diagnosis, safety and comfort for patients. Since 1950s, remarkable efforts have been undertaken for the development of bio-medical implanted and wireless telemetry bio-devices. Issues such as design of suitable modulation methods, use of power and monitoring devices, transfer energy from external to internal parts with high efficiency and high data rates and low power consumption all play an important role in the development of implantable devices. This paper provides a comprehensive survey on various modulation and demodulation techniques such as amplitude shift keying (ASK), frequency shift keying (FSK) and phase shift keying (PSK) of the existing wireless implanted devices. The details of specifications, including carrier frequency, CMOS size, data rate, power consumption and supply, chip area and application of the various modulation schemes of the implanted devices are investigated and summarized in the tables along with the corresponding key references. Current challenges and problems of the typical modulation applications of these technologies are illustrated with a brief suggestions and discussion for the progress of implanted device research in the future. It is observed that the prime requisites for the good quality of the implanted devices and their reliability are the energy transformation, data rate, CMOS size, power consumption and operation frequency. This review will hopefully lead to increasing efforts towards the development of low powered, high efficient, high data rate and reliable implanted devices

Wireless Power Transfer System for Battery-Less Body Implantable Devices

Department of Electrical EngineeringAs the life expectancy is increased and the welfare is promoted, researches on the body implantable medical devices (BIMD) are actively being carried out, and products providing more various functions are being released. On the other hand, due to these various functions, the power consumption of the BIMD is also increased, so that the primary battery alone cannot provide sufficient power for the devices. The limited capacity and life time of batteries force patients to make an additional payment and suffering for the power supply of the BIMD. Wireless power transfer technology is the technology which has been making remarkable progress mainly in wireless charging for personal portable devices and electric vehicles. Convergence of wireless power transfer technology (WPT) and rechargeable battery can extend the life time of the BIMD and reduce the suffering and the cost for battery replacements. Furthermore, WPT enables the devices which do not need to operate consistently such as body implantable sensor devices to be used without batteries. In this dissertation, techniques to support WPT for BIMD are introduced and proposed. First, basic researches on magnetic coupled WPT are presented. The basics which are important factors to analyze power transmission are introduced. In addition, circuits that make up the WPT system are described. There are three common technical challenges in WPT. Those are efficiency degradation on coil geometry, voltage gain variation with coil geometry, and power losses in WPT. The common challenges are discussed in chapter II. Moreover, additional challenges which are arisen in WPT for BIMD and approaches to resolve the challenges are addressed in chapter II. Then, efficiency improvement techniques and control techniques in WPT are presented in chapter III. The presented techniques to improve efficiency are applied in coil parts and circuit parts. In coil parts, efficiency enhancement technique by geometric variation is proposed. In circuit parts, instantaneous power consuming technique for step-down converter is suggested. Li-ion battery charger is also discussed in chapter III. Additionally, the wireless controlled constant current / constant voltage charging mode and the proposed step charging method are described. After that, WPT system for BIMD is discussed one by one with the proposed techniques for each part in chapter IV. A load transformation is suggested to improve efficiency in weak coupling, and suppress voltage gain variation under coil displacement. Power conversion efficiency improvement techniques for rectifier and converter are also proposed. By using the proposed technique for the converter, we can remove the bootstrap capacitors, and reduce the overall size of power circuits. In conclusion, techniques in coil parts and circuit parts to handle challenges in WPT for BIMD are fully investigated in this thesis in addition to the efficiency improvement and control techniques in common WPT. All the techniques are verified through simulations or experiments. The approaches realized in the thesis can be applied to other applications employing the WPT.clos