Design and simulation of a high-gain organic operational amplifier for use in quantification of cholesterol in low-cost point-of-care devices

© The Institution of Engineering and Technology. This paper presents circuit design and simulations of a high gain organic Op-Amp, for use in quantification of real cholesterol, in the range of 1-9 mM. A 7-stage inverter chain is added onto the design so as to enhance the amplifier gain. The circuit adapts p-channel transistors only (PMOS) design architecture with saturated loads, simulated on a conventional platform, using appropriate OTFT model and associated parameters. The effect of variation in threshold voltage on circuit operation is also examined. For a supply voltage of ±15 V, the DC output voltage is found to be within an acceptable range of -1 V to -12.5 V, with a highest open loop gain of 83 dB. The closed loop gain is also in agreement with theoretical values, in the range of 1.5 dB to 39 dB, with corresponding bandwidths of 770 Hz to 275 Hz respectively. The latter gain of 39 dB and/or gain-bandwidth product of 10.63 kHz is currently the highest reported in the literature, for this lower supply voltage. The amplifier offers adequate quantification factor, with linear sensitivity of -0.7 V/mM. This paper is the first to adapt organic circuit designs in quantification of cholesterol, with promising outputs, for implementation in low-cost sensor systems

A Second-Order ΣΔ ADC using sputtered IGZO TFTs with multilayer dielectric

This dissertation combines materials science and electronics engineering to implement, for the first time, a 2nd-order ∑∆ ADC using oxide TFTs. The transistors employ a sputtered IGZO semiconductor and an optimizeddielectric layer, based on mixtures of sputtered Ta2O5and SiO2. These dielectrics are studied in multilayer configurations, being the best results achieved for 7 layers: IG7.5 MV/cm, while keeping κ>10, yielding a major improvement over Ta2O5single-layer. After annealing at 200 °C, TFTs with these dielectrics exhibit μSAT≈13 cm2/Vs, On/Off≈107and S≈0.2 V/dec. An a-Si:H TFT RPI model is adapted to simulate these devices with good fitting to experimental data. Concerning circuits, the ∑∆ architecture is naturally selected to deal with device mismatch. After design optimization, ADC simulations achieve SNDR≈57 dB, DR≈65 dB and power dissipation, approximately, of 22 mW (VDD=10 V), which are above the current state-of-the-art for competing thinfilm technologies, such as organics or even LTPS. Mask layouts are currently under verification to enable successful circuit fabrication in the next months.This work is a major step towards the design of complex multifunctional electronic systems with oxide TFT technology, being integrated in ongoing EU-funded and FCT-funded research projects at CENIMAT and UNINOVA

Collective Communications and Computation Mechanisms on the RF Channel for Organic Printed Smart Labels and Resource-limited IoT Nodes

Radio Frequency IDentification (RFID) and Wireless Sensor Networks (WSN) are seen as enabler technologies for realizing the Internet of Things (IoT). Organic and printed Electronics (OE) has the potential to provide low cost and all-printable smart RFID labels in high volumes. With regard to WSN, power harvesting techniques and resource-efficient communications are promising key technologies to create sustainable and for the environment friendly sensing devices. However, the implementation of OE smart labels is only allowing printable devices of ultra-low hardware complexity, that cannot employ standard RFID communications. And, the deployment of current WSN technology is far away from offering battery-free and low-cost sensing technology. To this end, the steady growth of IoT is increasing the demand for more network capacity and computational power. With respect to wireless communications research, the state-of-the-art employs superimposed radio transmission in form of physical layer network coding and computation over the MAC to increase information flow and computational power, but lacks on practicability and robustness so far. With regard to these research challenges we developed in particular two approaches, i.e., code-based Collective Communications for dense sensing environments, and time-based Collective Communications (CC) for resource-limited WSNs. In respect to the code-based CC approach we exploit the principle of superimposed radio transmission to acquire highly scalable and robust communications obtaining with it at the same time as well minimalistic smart RFID labels, that can be manufactured in high volume with present-day OE. The implementation of our code-based CC relies on collaborative and simultaneous transmission of randomly drawn burst sequences encoding the data. Based on the framework of hyper-dimensional computing, statistical laws and the superposition principle of radio waves we obtained the communication of so called ensemble information, meaning the concurrent bulk reading of sensed values, ranges, quality rating, identifiers (IDs), and so on. With 21 transducers on a small-scale reader platform we tested the performance of our approach successfully proving the scalability and reliability. To this end, we implemented our code-based CC mechanism into an all-printable passive RFID label down to the logic gate level, indicating a circuit complexity of about 500 transistors. In respect to time-based CC approach we utilize the superimposed radio transmission to obtain resource-limited WSNs, that can be deployed in wide areas for establishing, e.g., smart environments. In our application scenario for resource-limited WSN, we utilize the superimposed radio transmission to calculate functions of interest, i.e., to accomplish data processing directly on the radio channel. To prove our concept in a case study, we created a WSN with 15 simple nodes measuring the environmental mean temperature. Based on our analysis about the wireless computation error we were able to minimize the stochastic error arbitrarily, and to remove the systematic error completely

Ultra-thin and flexible CMOS technology: ISFET-based microsystem for biomedical applications

A new paradigm of silicon technology is the ultra-thin chip (UTC) technology and the emerging applications. Very thin integrated circuits (ICs) with through-silicon vias (TSVs) will allow the stacking and interconnection of multiple dies in a compact format allowing a migration towards three-dimensional ICs (3D-ICs). Also, extremely thin and therefore mechanically bendable silicon chips in conjunction with the emerging thin-film and organic semiconductor technologies will enhance the performance and functionality of large-area flexible electronic systems. However, UTC technology requires special attention related to the circuit design, fabrication, dicing and handling of ultra-thin chips as they have different physical properties compared to their bulky counterparts. Also, transistors and other active devices on UTCs experiencing variable bending stresses will suffer from the piezoresistive effect of silicon substrate which results in a shift of their operating point and therefore, an additional aspect should be considered during circuit design. This thesis tries to address some of these challenges related to UTC technology by focusing initially on modelling of transistors on mechanically bendable Si-UTCs. The developed behavioural models are a combination of mathematical equations and extracted parameters from BSIM4 and BSIM6 modified by a set of equations describing the bending-induced stresses on silicon. The transistor models are written in Verilog-A and compiled in Cadence Virtuoso environment where they were simulated at different bending conditions. To complement this, the verification of these models through experimental results is also presented. Two chips were designed using a 180 nm CMOS technology. The first chip includes nMOS and pMOS transistors with fixed channel width and two different channel lengths and two different channel orientations (0° and 90°) with respect to the wafer crystal orientation. The second chip includes inverter logic gates with different transistor sizes and orientations, as in the previous chip. Both chips were thinned down to ∼20m using dicing-before-grinding (DBG) prior to electrical characterisation at different bending conditions. Furthermore, this thesis presents the first reported fully integrated CMOS-based ISFET microsystem on UTC technology. The design of the integrated CMOS-based ISFET chip with 512 integrated on-chip ISFET sensors along with their read-out and digitisation scheme is presented. The integrated circuits (ICs) are thinned down to ∼30m and the bulky, as well as thinned ICs, are electrically and electrochemically characterised. Also, the thesis presents the first reported mechanically bendable CMOS-based ISFET device demonstrating that mechanical deformation of the die can result in drift compensation through the exploitation of the piezoresistive nature of silicon. Finally, this thesis presents the studies towards the development of on-chip reference electrodes and biodegradable and ultra-thin biosensors for the detection of neurotransmitters such as dopamine and serotonin

Feature Papers in Electronic Materials Section

This book entitled "Feature Papers in Electronic Materials Section" is a collection of selected papers recently published on the journal Materials, focusing on the latest advances in electronic materials and devices in different fields (e.g., power- and high-frequency electronics, optoelectronic devices, detectors, etc.). In the first part of the book, many articles are dedicated to wide band gap semiconductors (e.g., SiC, GaN, Ga2O3, diamond), focusing on the current relevant materials and devices technology issues. The second part of the book is a miscellaneous of other electronics materials for various applications, including two-dimensional materials for optoelectronic and high-frequency devices. Finally, some recent advances in materials and flexible sensors for bioelectronics and medical applications are presented at the end of the book

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book