A self-powered single-chip wireless sensor platform

Internet of things” require a large array of low-cost sensor nodes, wireless connectivity, low power operation and system intelligence. On the other hand, wireless biomedical implants demand additional specifications including small form factor, a choice of wireless operating frequencies within the window for minimum tissue loss and bio-compatibility This thesis describes a low power and low-cost internet of things system suitable for implant applications that is implemented in its entirety on a single standard CMOS chip with an area smaller than 0.5 mm2. The chip includes integrated sensors, ultra-low-power transceivers, and additional interface and digital control electronics while it does not require a battery or complex packaging schemes. It is powered through electromagnetic (EM) radiation using its on-chip miniature antenna that also assists with transmit and receive functions. The chip can operate at a short distance (a few centimeters) from an EM source that also serves as its wireless link. Design methodology, system simulation and optimization and early measurement results are presented

RF Energy Harvesting Techniques for Battery-less Wireless Sensing, Industry 4.0 and Internet of Things: A Review

As the Internet of Things (IoT) continues to expand, the demand for the use of energy-efficient circuits and battery-less devices has grown rapidly. Battery-less operation, zero maintenance and sustainability are the desired features of IoT devices in fifth generation (5G) networks and green Industry 4.0 wireless systems. The integration of energy harvesting systems, IoT devices and 5G networks has the potential impact to digitalize and revolutionize various industries such as Industry 4.0, agriculture, food, and healthcare, by enabling real-time data collection and analysis, mitigating maintenance costs, and improving efficiency. Energy harvesting plays a crucial role in envisioning a low-carbon Net Zero future and holds significant political importance. This survey aims at providing a comprehensive review on various energy harvesting techniques including radio frequency (RF), multi-source hybrid and energy harvesting using additive manufacturing technologies. However, special emphasis is given to RF-based energy harvesting methodologies tailored for battery-free wireless sensing, and powering autonomous low-power electronic circuits and IoT devices. The key design challenges and applications of energy harvesting techniques, as well as the future perspective of System on Chip (SoC) implementation, data digitization in Industry 4.0, next-generation IoT devices, and 5G communications are discussed

Next-generation IoT devices: sustainable eco-friendly manufacturing, energy harvesting, and wireless connectivity

This invited paper presents potential solutions for tackling some of the main underlying challenges toward developing sustainable Internet-of-things (IoT) devices with a focus on eco-friendly manufacturing, sustainable powering, and wireless connectivity for next-generation IoT devices. The diverse applications of IoT systems, such as smart cities, wearable devices, self-driving cars, and industrial automation, are driving up the number of IoT systems at an unprecedented rate. In recent years, the rapidly-increasing number of IoT devices and the diverse application-specific system requirements have resulted in a paradigm shift in manufacturing processes, powering methods, and wireless connectivity solutions. The traditional cloud-centering IoT systems are moving toward distributed intelligence schemes that impose strict requirements on IoT devices, e.g., operating range, latency, and reliability. In this article, we provide an overview of hardware-related research trends and application use cases of emerging IoT systems and highlight the enabling technologies of next-generation IoT. We review eco-friendly manufacturing for next-generation IoT devices, present alternative biodegradable and eco-friendly options to replace existing materials, and discuss sustainable powering IoT devices by exploiting energy harvesting and wireless power transfer. Finally, we present (ultra-)low-power wireless connectivity solutions that meet the stringent energy efficiency and data rate requirements of future IoT systems that are compatible with a batteryless operation

Modulated Backscatter for Low-Power High-Bandwidth Communication

<p>This thesis re-examines the physical layer of a communication link in order to increase the energy efficiency of a remote device or sensor. Backscatter modulation allows a remote device to wirelessly telemeter information without operating a traditional transceiver. Instead, a backscatter device leverages a carrier transmitted by an access point or base station.</p><p>A low-power multi-state vector backscatter modulation technique is presented where quadrature amplitude modulation (QAM) signalling is generated without running a traditional transceiver. Backscatter QAM allows for significant power savings compared to traditional wireless communication schemes. For example, a device presented in this thesis that implements 16-QAM backscatter modulation is capable of streaming data at 96 Mbps with a radio communication efficiency of 15.5 pJ/bit. This is over 100x lower energy per bit than WiFi (IEEE 802.11).</p><p>This work could lead to a new class of high-bandwidth sensors or implantables with power consumption far lower than traditional radios.</p>Dissertatio

Tri-band CMOS Circuit Dedicated for Ambient RF Energy Harvesting

RÉSUMÉ L'utilisation de systèmes sans fil connait une croissance rapide dans divers domaines tels que les réseaux de téléphonie cellulaire, Wi-Fi, Wi-Max, la radiodiffusion et les communications par satellite. Cette croissance mènera à une quantité considérable d'énergie électromagnétique générée dans l'air ambiant, mais toujours en dessous des limites de sécurité internationales. Ainsi, la recherche au niveau des systèmes de récupération d'énergie RF pour alimenter des appareils électroniques miniaturisés à faible consommation de puissance devient attrayante et prometteuse. Le bloc principal dans un système de récupération d'énergie RF est le redresseur qui détermine l'efficacité et la sensibilité de l'ensemble du système. Étant donné que la puissance RF ambiante est très faible, la quantité d'énergie captée par l'antenne l’est également. En outre, il y a des pertes au niveau du réseau d'adaptation d’impédance qui réduisent encore plus la puissance transmise au bloc redresseur. Par conséquent, la puissance disponible est trop faible pour faire fonctionner des redresseurs classiques. Dans ce mémoire, nous proposons trois redresseurs à trois-étages et à grilles totalement croisées-couplées en utilisant des transistors à faible tension de seuil afin d’opérer à de faibles puissances d'entrée. Les trois redresseurs ont été conçus et intégrés au sein d’une même puce fabriquée en utilisant une technologie CMOS 130nm d’IBM. Ils ont été optimisés à des fréquences de 880MHz, 1960MHz et 2.45GHz respectivement. Les résultats expérimentaux démontrent qu’ils atteignent une efficacité de conversion de puissance maximale de 62%, 62% et 56.2% respectivement. Les mesures montrent également une grande amélioration de l'efficacité à de faibles niveaux de puissance d'entrée. Afin de récupérer l'énergie ambiante de trois principales sources RF au Canada – GSM-850, GSM-1900 et Wi-Fi, un système de redresseur utilisé pour la combinaison de la puissance de ces trois canaux est simulé et analysé. Le système utilise une topologie consistant simplement à connecter les sorties des redresseurs ensemble pour charger le condensateur de charge. En dépit de la grande amélioration de l'efficacité et de la sensibilité dans la plage de 0-5μW, une baisse d'efficacité indésirable se produit aux puissances plus élevées. Ainsi, un nouveau bloc de gestion de l'alimentation est proposé. De plus, une antenne tri-bande est conçue et simulée pour diminuer le volume de l'ensemble du système de récupération d'énergie RF. En particulier, les pertes par réflexion obtenues sont de -25.43dB, -13.92dB et -12.73dB aux fréquences citées plus haut respectivement.---------- ABSTRACT Nowadays, the use of wireless systems has grown rapidly in various domains such as cellular phone networks, Wi-Fi, Wi-Max, radio broadcasting and satellite communications. The growing use of these wireless systems leads to considerable amount of electromagnetic energy generated in ambient air (of course, still below international safety limits). Thus the research in ambient RF energy harvesting system dedicated for powering up low-power-consumption miniaturized electronic devices becomes attractive and promising. The main block in a RF harvesting system is the rectifier which determines the efficiency and sensitivity of the whole system. Since ambient RF power is very low, the amount of power captured by the antenna is extremely low. Besides, there is loss on matching networks, thus the available power given to the rectifier block is too low for traditional rectifiers to operate. Therefore, in this master thesis, three three-stage fully gate cross-coupled rectifiers using low-thresholdvoltage transistors are proposed to overcome the dead zone in low input power range. The three rectifiers optimized at 880MHz, 1960MHz and 2.45GHz frequencies respectively are designed on one chip layout. Their experimental results are retrieved from this custom fabricated integrated circuit using IBM 130nm CMOS technology. They achieve peak efficiencies of 62%, 62% and 56.2% respectively and show great improvements on power conversion efficiency at low input power level. In order to harvest ambient RF energy from the three main RF contributors in Canada – GSM-850, GSM-1900 and Wi-Fi 2.4GHz, a rectifier system used for power combination from these three channels is simulated and analyzed. The system employs a simple topology by connecting the outputs together to charge the load capacitor. In spite of its high improvements on efficiency and sensitivity in 0-5μW range, an undesirable efficiency drop happens at higher input power levels. Thus an idea of power management block is proposed. In addition, a tri-band antenna is designed and simulated so as to decrease the volume of the overall RF energy harvesting system. It achieves return loss of -25.43dB, -13.92dB and - 12.73dB at each desired band respectively

Application of Ultra-Wideband Technology to RFID and Wireless Sensors

Aquesta Tesi Doctoral estudia l'ús de tecnologia de ràdio banda ultraampla (UWB) per sistemes de identificació per radiofreqüència (RFID) i sensors sense fils. Les xarxes de sensors sense fils (WSNs), ciutats i llars intel•ligents, i, en general, l'Internet de les coses (IoT) requereixen interfícies de ràdio simples i de baix consum i cost per un número molt ampli de sensors disseminats. UWB en el domini temporal es proposa aquí com una tecnologia de radio habilitant per aquestes aplicacions. Un model circuital s'estudia per RFID d'UWB codificat en el temps. Es proposen lectors basats en ràdars polsats comercials amb tècniques de processat de senyal. Tags RFID sense xip (chipless) codificats en el temps son dissenyats i caracterizats en termes de número d'identificacions possible, distància màxima de lectura, polarització, influència de materials adherits, comportament angular i corbatura del tag. Es proposen sensors chipless de temperatura i composició de ciment (mitjançant detecció de permitivitat). Dos plataformes semipassives codificades en temps (amb un enllaç paral•lel de banda estreta per despertar el sensor i estalviar energia) es proposen com solucions més complexes i robustes, amb una distància de lectura major. Es dissenya un sensor de temperatura (alimentat per energia solar) i un sensor de diòxid de nitrogen (mitjançant nanotubs de carboni i alimentat per una petita bateria), ambdòs semipassius amb circuiteria analògica. Es dissenya un multi-sensor semipassiu capaç de mesurar temperatura, humitat, pressió i acceleració, fent servir un microcontrolador de baix consum digital. Combinant els tags RFID UWB codificats en temps amb tecnologia de ràdar de penetració del terra (GPR), es deriva una aplicació per localització en interiors amb terra intel•ligent. Finalment, dos sistemes actius RFID UWB codificats en el temps s'estudien per aplicacions de localització de molt llarg abast.Esta Tesis Doctoral estudia el uso de tecnología de radio de banda ultraancha (UWB) para sistemas de identificación por radiofrecuencia (RFID) y sensores inalámbricos. Las redes de sensores inalámbricas (WSNs), ciudades y casas inteligentes, y, en general, el Internet de las cosas (IoT) requieren de interfaces de radio simples y de bajo consumo y coste para un número muy amplio de sensores diseminados. UWB en el dominio temporal se propone aquí como una tecnología de radio habilitante para dichas aplicaciones. Un modelo circuital se estudia para RFID de UWB codificado en tiempo. Configuraciones de lector, basadas en rádar pulsados comerciales, son propuestas, además de técnicas de procesado de señal. Tags RFID sin chip (chipless) codificados en tiempo son diseñados y caracterizados en términos de número de identificaciones posible, distancia máxima de lectura, polarización, influencia de materiales adheridos, comportamiento angular y curvatura del tag. Se proponen sensores chipless de temperatura y composición de cemento (mediante detección de permitividad). Dos plataformas semipasivas codificadas en tiempo (con un enlace paralelo de banda estrecha para despertar el sensor y ahorrar energía) se proponen como soluciones más complejas y robustas, con una distancia de lectura mayor. Se diseña un sensor de temperatura (alimentado por energía solar) y un sensor de dióxido de nitrógeno (mediante nanotubos de carbono y alimentado por una batería pequeña), ambos semipasivos con circuitería analógica. Se diseña un multi-sensor semipasivo capaz de medir temperatura, humedad, presión y aceleración, usando un microcontrolador digital de bajo consumo. Combinando los tags RFID UWB codificados en tiempo y tecnología de radar de penetración de suelo (GPR), se deriva una aplicación para localización en interiores con suelo inteligente. Finalmente, dos sistemas activos RFID UWB codificados en tiempo se estudian para aplicaciones de localización de muy largo alcance.This Doctoral Thesis studies the use of ultra-wideband (UWB) radio technology for radio-frequency identification (RFID) and wireless sensors. Wireless sensor networks (WSNs) for smart cities, smart homes and, in general, Internet of Things (IoT) applications require low-power, low-cost and simple radio interfaces for an expected very large number of scattered sensors. UWB in time domain is proposed here as an enabling radio technology. A circuit model is studied for time-coded UWB RFID. Reader setups based on commercial impulse radars are proposed, in addition to signal processing techniques. Chipless time-coded RFID tags are designed and characterized in terms of number of possible IDs, maximum reading distance, polarization, influence of attached materials, angular behaviour and bending. Chipless wireless temperature sensors and chipless concrete composition sensors (enabled by permittivity sensing) are proposed. Two semi-passive time-coded RFID sensing platforms are proposed as more complex, more robust, and longer read-range solutions. A wake-up link is used to save energy when the sensor is not being read. A semi-passive wireless temperature sensor (powered by solar energy) and a wireless nitrogen dioxide sensor (enabled with carbon nanotubes and powered by a small battery) are developed, using analog circuitry. A semi-passive multi-sensor tag capable of measuring temperature, humidity, pressure and acceleration is proposed, using a digital low-power microcontroller. Combining time-coded UWB RFID tags and ground penetrating radar, a smart floor application for indoor localization is derived. Finally, as another approach, two active time-coded RFID systems are developed for very long-range applications

UWB Precise Indoor Localization System Performance, Limitations and its Integration

An indoor localization system that was built at University of Tennessee is extensively studied and improved. The goal of the system is to achieve mm down to sub-mm accuracy/precision. Sub-sampling is used to alleviate the high sampling rate required for UWB signals. Current commercial direct sampling systems are still too slow or prohibitively expensive for UWB applications. We developed two different sub-sampling techniques, but the two systems suffer numerous shortcomings: low throughput, non-robustness, non-linearity. A third system is introduced that achieve both high accuracy and high through-put. Changes in the detection algorithm and the frame synchronization are developed to accommodate the new scheme. We present our efforts to replace hybrid components by recently developed MMIC chips, and an integrated digital module developed by ULM University and UT respectively. Similar localization performance was achieved but rather with significantly reduced power consumption, much smaller footprints, and higher throughput. Step Recovery Diode (SRD) based UWB pulse generators suffer from jitter caused by AM-to-PM conversion, SRD shot noise and clock jitter. A mathematical model for simulation of the jitter and amplitude variation effect in the equivalent time sampling technique has been developed and used in SystemVue simulations. A criterion as an estimate of system accuracy is defined as Signal to Distortion Ratio (SDR) and used. Similarly, a model for AM and PM noise analysis for an SRD based UWB pulse generator is developed that was validated experimentally. We estimate the achievable system localization error. A mathematical model and simulation platform are developed to describe its behavior. Limits on the location accuracy as a function of the parameters of the UWB system are described. A discussion of the dominant reasons for errors that include picoseconds pulsar jitter, sampling clock jitter, sampling rate, and system additive white Gaussian noise (AWGN) is presented. We show a simple method to calculate the total system jitter, and describe error biasing phenomenon as the tag moves approaching one base-station and distancing another. Design curves are provided to determine the specifications of system components to achieve a certain positioning accuracy

Low-complexity, low-area computer architectures for cryptographic application in resource constrained environments

RCE (Resource Constrained Environment) is known for its stringent hardware design requirements. With the rise of Internet of Things (IoT), low-complexity and low-area designs are becoming prominent in the face of complex security threats. Two low-complexity, low-area cryptographic processors based on the ultimate reduced instruction set computer (URISC) are created to provide security features for wireless visual sensor networks (WVSN) by using field-programmable gate array (FPGA) based visual processors typically used in RCEs. The first processor is the Two Instruction Set Computer (TISC) running the Skipjack cipher. To improve security, a Compact Instruction Set Architecture (CISA) processor running the full AES with modified S-Box was created. The modified S-Box achieved a gate count reduction of 23% with no functional compromise compared to Boyar’s. Using the Spartan-3L XC3S1500L-4-FG320 FPGA, the implementation of the TISC occupies 71 slices and 1 block RAM. The TISC achieved a throughput of 46.38 kbps at a stable 24MHz clock. The CISA which occupies 157 slices and 1 block RAM, achieved a throughput of 119.3 kbps at a stable 24MHz clock. The CISA processor is demonstrated in two main applications, the first in a multilevel, multi cipher architecture (MMA) with two modes of operation, (1) by selecting cipher programs (primitives) and sharing crypto-blocks, (2) by using simple authentication, key renewal schemes, and showing perceptual improvements over direct AES on images. The second application demonstrates the use of the CISA processor as part of a selective encryption architecture (SEA) in combination with the millions instructions per second set partitioning in hierarchical trees (MIPS SPIHT) visual processor. The SEA is implemented on a Celoxica RC203 Vertex XC2V3000 FPGA occupying 6251 slices and a visual sensor is used to capture real world images. Four images frames were captured from a camera sensor, compressed, selectively encrypted, and sent over to a PC environment for decryption. The final design emulates a working visual sensor, from on node processing and encryption to back-end data processing on a server computer

Sensors and Systems for Indoor Positioning

This reprint is a reprint of the articles that appeared in Sensors' (MDPI) Special Issue on “Sensors and Systems for Indoor Positioning". The published original contributions focused on systems and technologies to enable indoor applications

Low-complexity, low-area computer architectures for cryptographic application in resource constrained environments

RCE (Resource Constrained Environment) is known for its stringent hardware design requirements. With the rise of Internet of Things (IoT), low-complexity and low-area designs are becoming prominent in the face of complex security threats. Two low-complexity, low-area cryptographic processors based on the ultimate reduced instruction set computer (URISC) are created to provide security features for wireless visual sensor networks (WVSN) by using field-programmable gate array (FPGA) based visual processors typically used in RCEs. The first processor is the Two Instruction Set Computer (TISC) running the Skipjack cipher. To improve security, a Compact Instruction Set Architecture (CISA) processor running the full AES with modified S-Box was created. The modified S-Box achieved a gate count reduction of 23% with no functional compromise compared to Boyar’s. Using the Spartan-3L XC3S1500L-4-FG320 FPGA, the implementation of the TISC occupies 71 slices and 1 block RAM. The TISC achieved a throughput of 46.38 kbps at a stable 24MHz clock. The CISA which occupies 157 slices and 1 block RAM, achieved a throughput of 119.3 kbps at a stable 24MHz clock. The CISA processor is demonstrated in two main applications, the first in a multilevel, multi cipher architecture (MMA) with two modes of operation, (1) by selecting cipher programs (primitives) and sharing crypto-blocks, (2) by using simple authentication, key renewal schemes, and showing perceptual improvements over direct AES on images. The second application demonstrates the use of the CISA processor as part of a selective encryption architecture (SEA) in combination with the millions instructions per second set partitioning in hierarchical trees (MIPS SPIHT) visual processor. The SEA is implemented on a Celoxica RC203 Vertex XC2V3000 FPGA occupying 6251 slices and a visual sensor is used to capture real world images. Four images frames were captured from a camera sensor, compressed, selectively encrypted, and sent over to a PC environment for decryption. The final design emulates a working visual sensor, from on node processing and encryption to back-end data processing on a server computer