Database machines in support of very large databases

Software database management systems were developed in response to the needs of early data processing applications. Database machine research developed as a result of certain performance deficiencies of these software systems. This thesis discusses the history of database machines designed to improve the performance of database processing and focuses primarily on the Teradata DBC/1012, the only successfully marketed database machine that supports very large databases today. Also reviewed is the response of IBM to the performance needs of its database customers; this response has been in terms of improvements in both software and hardware support for database processing. In conclusion, an analysis is made of the future of database machines, in particular the DBC/1012, in light of recent IBM enhancements and its immense customer base

MPSoCBench : um framework para avaliação de ferramentas e metodologias para sistemas multiprocessados em chip

Orientador: Rodolfo Jardim de AzevedoTese (doutorado) - Universidade Estadual de Campinas, Instituto de ComputaçãoResumo: Recentes metodologias e ferramentas de projetos de sistemas multiprocessados em chip (MPSoC) aumentam a produtividade por meio da utilização de plataformas baseadas em simuladores, antes de definir os últimos detalhes da arquitetura. No entanto, a simulação só é eficiente quando utiliza ferramentas de modelagem que suportem a descrição do comportamento do sistema em um elevado nível de abstração. A escassez de plataformas virtuais de MPSoCs que integrem hardware e software escaláveis nos motivou a desenvolver o MPSoCBench, que consiste de um conjunto escalável de MPSoCs incluindo quatro modelos de processadores (PowerPC, MIPS, SPARC e ARM), organizado em plataformas com 1, 2, 4, 8, 16, 32 e 64 núcleos, cross-compiladores, IPs, interconexões, 17 aplicações paralelas e estimativa de consumo de energia para os principais componentes (processadores, roteadores, memória principal e caches). Uma importante demanda em projetos MPSoC é atender às restrições de consumo de energia o mais cedo possível. Considerando que o desempenho do processador está diretamente relacionado ao consumo, há um crescente interesse em explorar o trade-off entre consumo de energia e desempenho, tendo em conta o domínio da aplicação alvo. Técnicas de escalabilidade dinâmica de freqüência e voltagem fundamentam-se em gerenciar o nível de tensão e frequência da CPU, permitindo que o sistema alcance apenas o desempenho suficiente para processar a carga de trabalho, reduzindo, consequentemente, o consumo de energia. Para explorar a eficiência energética e desempenho, foram adicionados recursos ao MPSoCBench, visando explorar escalabilidade dinâmica de voltaegem e frequência (DVFS) e foram validados três mecanismos com base na estimativa dinâmica de energia e taxa de uso de CPUAbstract: Recent design methodologies and tools aim at enhancing the design productivity by providing a software development platform before the definition of the final Multiprocessor System on Chip (MPSoC) architecture details. However, simulation can only be efficiently performed when using a modeling and simulation engine that supports system behavior description at a high abstraction level. The lack of MPSoC virtual platform prototyping integrating both scalable hardware and software in order to create and evaluate new methodologies and tools motivated us to develop the MPSoCBench, a scalable set of MPSoCs including four different ISAs (PowerPC, MIPS, SPARC, and ARM) organized in platforms with 1, 2, 4, 8, 16, 32, and 64 cores, cross-compilers, IPs, interconnections, 17 parallel version of software from well-known benchmarks, and power consumption estimation for main components (processors, routers, memory, and caches). An important demand in MPSoC designs is the addressing of energy consumption constraints as early as possible. Whereas processor performance comes with a high power cost, there is an increasing interest in exploring the trade-off between power and performance, taking into account the target application domain. Dynamic Voltage and Frequency Scaling techniques adaptively scale the voltage and frequency levels of the CPU allowing it to reach just enough performance to process the system workload while meeting throughput constraints, and thereby, reducing the energy consumption. To explore this wide design space for energy efficiency and performance, both for hardware and software components, we provided MPSoCBench features to explore dynamic voltage and frequency scalability (DVFS) and evaluated three mechanisms based on energy estimation and CPU usage rateDoutoradoCiência da ComputaçãoDoutora em Ciência da Computaçã

Image and video processing using graphics hardware

Graphic Processing Units have during the recent years evolved into inexpensive high-performance many-core computing units. Earlier being accessible only by graphic APIs, new hardware architectures and programming tools have made it possible to program these devices using arbitrary data types and standard languages like C. This thesis investigates the development process and performance of image and video processing algorithms on graphic processing units, regardless of vendors. The tool used for programming the graphic processing units is OpenCL, a rela- tively new specification for heterogenous computing. Two image algorithms are investigated, bilateral filter and histogram. In addition, an attempt have been tried to make a template-based solution for generation and auto-optimalization of device code, but this approach seemed to have some shortcomings to be usable enough at this time

Goddard Conference on Mass Storage Systems and Technologies, Volume 1

Copies of nearly all of the technical papers and viewgraphs presented at the Goddard Conference on Mass Storage Systems and Technologies held in Sep. 1992 are included. The conference served as an informational exchange forum for topics primarily relating to the ingestion and management of massive amounts of data and the attendant problems (data ingestion rates now approach the order of terabytes per day). Discussion topics include the IEEE Mass Storage System Reference Model, data archiving standards, high-performance storage devices, magnetic and magneto-optic storage systems, magnetic and optical recording technologies, high-performance helical scan recording systems, and low end helical scan tape drives. Additional topics addressed the evolution of the identifiable unit for processing purposes as data ingestion rates increase dramatically, and the present state of the art in mass storage technology

Performance evaluation of distributed systems with unbalanced flows : an analysis of the INFOPLEX data storage hierarchy

Thesis (Ph. D.)--Massachusetts Institute of Technology, Sloan School of Management, 1985.MICROFICHE COPY AVAILABLE IN ARCHIVES AND DEWEY.Bibliography: leaves 165-171.by Yng-Yuh Richard Wang.Ph.D

Advanced Lease Caching

Since the dawn of computing, CPU performance has continually grown, buoyed by Moore\u27s Law. Execution speed for parallelizable programs in particular has massively increased with the now widespread employment of GPUs, TPUs, and FPGAs, capable of preforming hundreds of computations simultaneously, for data processing. A major bottleneck for further performance increases, which has impeded speedup of sequential programming in particular, is the processor memory performance gap. One of the approaches to address this block is improving cache management algorithms. Caching is transparent to software, but traditional caching algorithms forgo hardware-software collaboration. Previous work introduced the idea of assigning leases to cache blocks as a form of collaborative cache eviction policy and introduced two lease-caching algorithms, Compiler Lease of cAche Memory (CLAM) and Phased Reference Leasing (PRL), evaluating them over 7 benchmarks from the Polybench benchmark suite. This work evaluates CLAM and PRL over all thirty benchmarks of the Polybench suite for multiple dataset sizes. Additionally, to address the flaws CLAM and PRL, two new lease-caching algorithms have been developed: Scoped Hooked Eviction Lease (SHEL) and Cross-Scope Eviction Lease (C-SHEL). These algorithms are evaluated not just for a single-level cache, typically found in embedded systems, but also for a multi-level cache as exists in more high-performance systems including multi-core CPUs. The test system uses a RISCV architecture to run benchmarks. All four lease caching algorithms outperform the baseline Pseudo Least Recently Used (PLRU) policy at both levels of the cache hierarchy. Further, SHEL and C-SHEL display significant performance increases over PRL for certain benchmarks, demonstrating the value of scoped leasing in addressing complex reuse interval (RI) behavior

Schedulability Analysis for the Abort-and-Restart Model

In real-time systems, a schedulable task-set guarantees that all tasks complete before their deadlines. In functional programming, atomic execution provides the correctness of the program. Priority-based functional reactive programming (P-FRP) allows the usage of functional programming in the real-time system environment. The abort-and-restart (AR) is a scheme to implement P-FRP but an appropriate scheduling approach does not exist at the moment. Hence, efficient analysis is needed for the AR model. In this thesis, the schedulability analysis for the AR model is introduced and it shows that finding the critical instant for the AR model with periodic and sporadic tasks is intractable, and a new formulation is derived. Afterwards, a new priority assignment scheme is developed that has the performance close to the exhaustive search method, which is intractable for large systems. The technique of deferred preemption is employed and a new model, deferred abort (DA), provides better schedulability and dominates the non-preemptive model. Lastly, a tighter analysis is introduced and the technique of the multi-set approach from the analysis of cache related preemption delay is employed to introduce a new approach, multi-bag. The multi-bag approach can apply to both the AR model and the DA model. In the experiments, the schedulability of the AR model is improved at each stage of the research in this thesis

Model Checking and Model-Based Testing : Improving Their Feasibility by Lazy Techniques, Parallelization, and Other Optimizations

This thesis focuses on the lightweight formal method of model-based testing for checking safety properties, and derives a new and more feasible approach. For liveness properties, dynamic testing is impossible, so feasibility is increased by specializing on an important class of properties, livelock freedom, and deriving a more feasible model checking algorithm for it. All mentioned improvements are substantiated by experiments