Selective SWIFT-R. A Flexible Software-Based Technique for Soft Error Mitigation in Low-Cost Embedded Systems

Commercial off-the-shelf microprocessors are the core of low-cost embedded systems due to their programmability and cost-effectiveness. Recent advances in electronic technologies have allowed remarkable improvements in their performance. However, they have also made microprocessors more susceptible to transient faults induced by radiation. These non-destructive events (soft errors), may cause a microprocessor to produce a wrong computation result or lose control of a system with catastrophic consequences. Therefore, soft error mitigation has become a compulsory requirement for an increasing number of applications, which operate from the space to the ground level. In this context, this paper uses the concept of selective hardening, which is aimed to design reduced-overhead and flexible mitigation techniques. Following this concept, a novel flexible version of the software-based fault recovery technique known as SWIFT-R is proposed. Our approach makes possible to select different registers subsets from the microprocessor register file to be protected on software. Thus, design space is enriched with a wide spectrum of new partially protected versions, which offer more flexibility to designers. This permits to find the best trade-offs between performance, code size, and fault coverage. Three case studies have been developed to show the applicability and flexibility of the proposal.This work was funded by the Ministry of Science and Innovation in Spain with the project ‘RENASER+: Integral Analysis of Digital Circuits and Systems for Aerospace Applications’ (TEC2010-22095-C03-01)

Multi-Threaded Mitigation of Radiation-Induced Soft Errors in Bare-Metal Embedded Systems

This article presents a software protection technique against radiation-induced faults which is based on a multi-threaded strategy. Data triplication and instructions flow duplication or triplication techniques are used to improve system reliability and thus, ensure a correct system operation. To achieve this objective, a relaxed lockstep model to synchronize the execution of both, redundant threads and variables under protection on different processing units is defined. The evaluation was performed by means of simulated fault injection campaigns in a multi-core ARM system. Results show that despite being considered techniques that imply an evident overhead in memory and instructions (Duplication With Comparison and Re-Execution – DWC-R and Triple Modular Redundancy – TMR), spreading the replicas in different instruction flows not only produce similar results than classic techniques, but also improves the computational and recovery time in presence of soft-errors. In addition, this paper highlights the importance of protecting memory-allocated data, since the instruction flow triplication is not enough to improve the overall system reliability.This work was funded by the Spanish Ministry of Economy and Competitiveness and the European Regional Development Fund through the following projects: ‘Evaluación temprana de los efectos de radiación mediante simulación y virtualización. Estrategias de mitigación en arquitecturas de microprocesadores avanzados’, (Ref: ESP2015-68245-C4-3-P, MINECO/FEDER, UE)

Application-Based Analysis of Register File Criticality for Reliability Assessment in Embedded Microprocessors

There is an increasing concern to reduce the cost and overheads during the development of reliable systems. Selective protection of most critical parts of the systems represents a viable solution to obtain a high level of reliability at a fraction of the cost. In particular to design a selective fault mitigation strategy for processor-based systems, it is mandatory to identify and prioritize the most vulnerable registers in the register file as best candidates to be protected (hardened). This paper presents an application-based metric to estimate the criticality of each register from the microprocessor register file in microprocessor-based systems. The proposed metric relies on the combination of three different criteria based on common features of executed applications. The applicability and accuracy of our proposal have been evaluated in a set of applications running in different microprocessors. Results show a significant improvement in accuracy compared to previous approaches and regardless of the underlying architecture.This work was funded in part by the Spanish Ministry of Education, Culture and Sports with the project “Developing hybrid fault tolerance techniques for embedded microprocessors” (PHB2012-0158-PC)

Dependability Evaluation of COTS Microprocessors via On-Chip debugging facilities

Este artículo presenta una herramienta de inyección de fallos y la metodología para la realización de campañas de inyección de Single-Event-Upsets (SEUs) en microprocesadores Commercial-off-the-shelf (COTS). Este método utiliza las ventajas que ofrecen las infraestructuras de depuración de los microprocesadores actuales, además del depurador estándar de GNU (GDB) para la ejecución y depuración de los programas de pruebas. Los experimentos desarrollados sobre microprocesadores reales, así como en las máquinas virtuales, demuestran la viabilidad y la flexibilidad de la propuesta como una solución de bajo costo para evaluar la fiabilidad de los microprocesadores COTS.This paper presents a fault injection tool and methodology for performing Single-Event-Upsets (SEUs) injection campaigns on Commercial-off-the-shelf (COTS) microprocessors. This method takes advantage of the debug facilities of modern microprocessors along with standard GNU Debugger (GDB) for executing and debugging benchmarks. The developed experiments on real boards, as well as on virtual machines, demonstrate the feasibility and flexibility of the proposal as a low-cost solution for assessing the reliability of COTS microprocessors.Este trabajo fue financiado por el Ministerio español de Economía y Competitividad y el Fondo Europeo de Desarrollo Regional con el proyecto "Evaluación Temprana de los Efectos de radiación Mediante simulación y virtualización. Estrategias de mitigación en arquitecturas de microprocesadores Avanzados "(Ref: ESP2015-68245-C4-3-P MINECO / FEDER, UE), y la Universidad Nacional de Colombia con el proyecto "Desarrollo de software Una métrica de Vulnerabilidad de registros en Microprocesadores COTS" (Cod HERMES: 28433)

A Hardware-Software Approach for On-Line Soft Error Mitigation in Interrupt-Driven Applications

Integrity assurance of configuration data has a significant impact on microcontroller-based systems reliability. This is especially true when running applications driven by events which behavior is tightly coupled to this kind of data. This work proposes a new hybrid technique that combines hardware and software resources for detecting and recovering soft-errors in system configuration data. Our approach is based on the utilization of a common built-in microcontroller resource (timer) that works jointly with a software-based technique, which is responsible to periodically refresh the configuration data. The experiments demonstrate that non-destructive single event effects can be effectively mitigated with reduced overheads. Results show an important increase in fault coverage for SEUs and SETs, about one order of magnitude.This work was funded in part by the Spanish Ministry of Education, Culture and Sports with the project “Developing hybrid fault tolerance techniques for embedded microprocessors” (PHB2012–0158-PC)

Proyecto iris

Proyecto IRIS es un prototipo de un periférico USB que busca representar imágenes mostradas en la pantalla de un computador, dirigido a personas con limitaciones visuales, quienes pueden interpretarlas a través del tacto. El sistema recibe una imagen que se reconstruye en la mano de la persona por medio de vibraciones inducidas por la interacción entre el campo magnético proveniente de los electroimanes de la malla del periférico y un guante receptor construido con imanes. La imagen para ser enviada al periférico sufre un proceso que consiste en la traducción de los colores que componen la imagen en pulsaciones de diferentes frecuencias de campos electromagnéticos

Proyecto iris

Proyecto IRIS es un prototipo de un periférico USB que busca representar imágenes mostradas en la pantalla de un computador, dirigido a personas con limitaciones visuales, quienes pueden interpretarlas a través del tacto. El sistema recibe una imagen que se reconstruye en la mano de la persona por medio de vibraciones inducidas por la interacción entre el campo magnético proveniente de los electroimanes de la malla del periférico y un guante receptor construido con imanes. La imagen para ser enviada al periférico sufre un proceso que consiste en la traducción de los colores que componen la imagen en pulsaciones de diferentes frecuencias de campos electromagnéticos

Proyecto iris

Proyecto IRIS es un prototipo de un periférico USB que busca representar imágenes mostradas en la pantalla de un computador, dirigido a personas con limitaciones visuales, quienes pueden interpretarlas a través del tacto. El sistema recibe una imagen que se reconstruye en la mano de la persona por medio de vibraciones inducidas por la interacción entre el campo magnético proveniente de los electroimanes de la malla del periférico y un guante receptor construido con imanes. La imagen para ser enviada al periférico sufre un proceso que consiste en la traducción de los colores que componen la imagen en pulsaciones de diferentes frecuencias de campos electromagnéticos

Grid móvil para procesar imágenes médicas

El procesamiento de imágenes médicas ayuda a los profesionales de la medicina a tomar decisiones de diagnóstico y tratamiento de pacientes. Algunos de estos algoritmos requieren gran cantidad de recursos, por esto se pueden apoyar en la computación distribuida y la abundancia de dispositivos móviles ociosos. En un trabajo anterior, se seleccionó Boinc como Grid Móvil, no obstante, se requería modificar los algoritmos a ejecutar en dispositivos móviles para integrarlos a esta infraestructura. En el presente proyecto se abordó dicho problema junto con la compilación cruzada de la librería ITK para la arquitectura ARM y la división de imágenes para su procesamiento paralelo.Medical image processing helps health professionals make decisions to diagnose and treat patients. Some of these algorithms require large amounts of resources, this is why they can be supported by distributed computing and an abundant number of idle mobile devices. In a previous project, Boinc was selected as the infrastructure for the Mobile Grid, however, it was required to modify the algorithms that would be executed in the devices, in order to integrate them with the system. This project addressed this problem along with the cross compilation of ITK library for the ARM architecture and the division of images to be processed in parallel.Ingeniero (a) de SistemasPregrad

SHARC: An efficient metric for selective protection of software against soft errors

This paper presents a metric for the efficient application of selective hardening using software-based techniques against soft errors. It offers a method for selecting the resources to be protected obtaining maximum fault coverage with the minimum overhead. Common approaches are based on exhaustive exploration of the solution space or time-consuming fault injection campaigns. Contrarily, our Software based HARdening Criticality metric (SHARC) relies on early estimations of the impact that protection techniques will have on the global reliability of the application. SHARC estimations are based on features extracted from the dynamic analysis of source code and produce a prioritization of the resources involved accordingly. For assessing our approach two case studies were carried out using low-cost embedded microprocessors. Results were compared to traditional approaches like brute-force exploration and the Architectural Vulnerability Factor (AVF) metric. Experiments show that SHARC improves the results between 5% and 21% at a fraction of the effort.This work was funded by the Spanish Ministry of Economy and Competitiveness and the European Regional Development Fund with the project Evaluación temprana de los efectos de radiación mediante simulación y virtualización. Estrategias de mitigación en arquitecturas de microprocesadores avanzados (Ref: ESP2015-68245-C4-3-P MINECO/FEDER, UE)