Toughening and Heat-Resistant Modification of Degradable PLA/PBS-Based Composites by Using Glass Fiber/Silicon Dioxide Hybrid Fillers

In this paper, to enhance the toughness and heat resistance properties of polylactic acid (PLA)/polybutylene succinate (PBS) composites, the PLA/PBS matrix was modified by different glass fiber (GF), GF/SiO2, and GF/(Polyaluminium chloride) PAC fillers. Additionally, the effect of filler type, filler content, components interaction and composite structure on the mechanical and thermal properties of the PLA/PBS composites was researched. The results showed that the addition of GF, GF/SiO2 and GF/PAC make the PLA/PBS composites appear significantly higher mechanical properties compared with the pristine PLA/PBS composite. Among the different inorganic fillers, the 10%GF/1%SiO2 fillers showed excellent strengthening, toughening and heat resistant effects. Compared with the pristine PLA/PBS matrix, the tensile strength, elastic modulus, flexural strength, flexural modulus and Izod impact strength improved by 36.28%, 70.74%, 67.95%, 66.61% and 135.68%, respectively. Considering the above, when the weight loss rate was 50%, the thermal decomposition temperature of the 10%GF/1%SiO2 modified PLA/PBS composites was the highest 412.83 °C and its Vicat softening point was up to 116.8 °C. In a word, the 10%GF/1%SiO2 reinforced PLA/PBS composites exhibit excellent mechanical and thermal properties, which broadens the application of biodegradable materials in specific scenarios

An S/H circuit with parasitics optimized for IF-sampling

An IF-sampling S/H is presented, which adopts a flip-around structure, bottom-plate sampling technique and improved input bootstrapped switches. To achieve high sampling linearity over a wide input frequency range, the floating well technique is utilized to optimize the input switches. Besides, techniques of transistor load linearization and layout improvement are proposed to further reduce and linearize the parasitic capacitance. The S/H circuit has been fabricated in 0.18-μm CMOS process as the front-end of a 14 bit, 250 MS/s pipeline ADC. For 30 MHz input, the measured SFDR/SNDR of the ADC is 94.7 dB/68. 5dB, which can remain over 84.3 dB/65.4 dB for input frequency up to 400 MHz. The ADC presents excellent dynamic performance at high input frequency, which is mainly attributed to the parasitics optimized S/H circuit