Silicon Echoes: Non-Invasive Trojan and Tamper Detection using Frequency-Selective Impedance Analysis

The threat of chip-level tampering and its detection has been widely researched. Hardware Trojan insertions are prominent examples of such tamper events. Altering the placement and routing of a design or removing a part of a circuit for side-channel leakage/fault sensitivity amplification are other instances of such attacks. While semi- and fully-invasive physical verification methods can confidently detect such stealthy tamper events, they are costly, time-consuming, and destructive. On the other hand, virtually all proposed non-invasive side-channel methods suffer from noise and, therefore, have low confidence. Moreover, they require activating the tampered part of the circuit (e.g., the Trojan trigger) to compare and detect the modifications. In this work, we introduce a non-invasive post-silicon tamper detection technique applicable to different classes of tamper events at the chip level without requiring the activation of the malicious circuit. Our method relies on the fact that physical modifications (regardless of their physical, activation, or action characteristics) alter the impedance of the chip. Hence, characterizing the impedance can lead to the detection of the tamper events. To sense the changes in the impedance, we deploy known RF tools, namely, scattering parameters, in which we inject sine wave signals with high frequencies to the power distribution network (PDN) of the system and measure the “echo” of the signal. The reflected signals in various frequency bands reveal different tamper events based on their impact size on the die. To validate our claims, we performed measurements on several proof-of-concept tampered hardware implementations realized on FPGAs manufactured with a 28 nm technology. We further show that deploying the Dynamic Time Warping (DTW) distance can distinguish between tamper events and noise resulting from manufacturing process variation of different chips/boards. Based on the acquired results, we demonstrate that stealthy hardware Trojans, as well as sophisticated modifications of P&R, can be detected

Toxicity and protective effects of cerium oxide nanoparticles (Nanoceria) depending on their preparation method, particle size, cell type, and exposure route

Nanoceria (cerium oxide nanoparticles) toxicity is currently a concern because of its use in motor vehicles in order to reduce carbon monoxide (CO), nitrogen oxides (NOx), and hydrocarbons in exhaust gases. In addition, many questions arise with respect to its biomedical applications exploiting its potential to protect cells against irradiation and oxidative stress. Indeed, toxicology studies on nanoceria report results that seem contradictory, demonstrating toxic effects in some studies, protective effects in others, and sometimes little or no effect at all. The variability in the experimental setups and particle characterization makes these studies difficult to compare and the toxicity of newly developed nanoceria materials challenging to predict. This microreview aims to compare the toxicity of nanoceria in terms of preparation method, particle size, concentration, host organism, and exposure method

A Study of UV Resistance of a Water-based Polyurethane Lacquer Containing Nano Ceria

Cerium oxide (Ceria) nano particle, as photodegradation prevention agent was studied in water-based polyurethane clear coat  systems. Polyurethane coatings show superior weathering resistance compared with acrylic melamine systems. However, any chemical change has detrimental effects on the property profile of PU coatings. Coatings containing various amounts of cerium oxide nanoparticles were prepared and their weathering resistance was evaluated using simulated UV cabinet. To this end the extent and mechanism of degradation was studied utilizing UV-Vis and FTIR-ATR spectroscopy as well as DMTA analysis. The results revealed that Ceria nano particles with concentration of 1.44 % (wt) absorb beyond 92.5% of UV light of UV-B region and showed an efficiency of 2000 times as of organic UV absorbers

ChipletQuake: On-Die Digital Impedance Sensing for Chiplet and Interposer Verification

The increasing complexity and cost of manufacturing monolithic chips have driven the semiconductor industry toward chiplet-based designs, where smaller, modular chiplets are integrated onto a single interposer. While chiplet architectures offer significant advantages, such as improved yields, design flexibility, and cost efficiency, they introduce new security challenges in the horizontal hardware manufacturing supply chain. These challenges include risks of hardware Trojans, cross-die side-channel and fault injection attacks, probing of chiplet interfaces, and intellectual property theft. To address these concerns, this paper presents ChipletQuake, a novel on-chiplet framework for verifying the physical security and integrity of adjacent chiplets during the post-silicon stage. By sensing the impedance of the power delivery network (PDN) of the system, ChipletQuake detects tamper events in the interposer and neighboring chiplets without requiring any direct signal interface or additional hardware components. Fully compatible with the digital resources of FPGA-based chiplets, this framework demonstrates the ability to identify the insertion of passive and subtle malicious circuits, providing an effective solution to enhance the security of chiplet-based systems. To validate our claims, we showcase how our framework detects hardware Trojans and interposer tampering

Silicon Echoes: Non-Invasive Trojan and Tamper Detection using Frequency-Selective Impedance Analysis

The threat of chip-level tampering and its detection has been widely researched. Hardware Trojan insertions are prominent examples of such tamper events. Altering the placement and routing of a design or removing a part of a circuit for side-channel leakage/fault sensitivity amplification are other instances of such attacks. While semi- and fully-invasive physical verification methods can confidently detect such stealthy tamper events, they are costly, time-consuming, and destructive. On the other hand, virtually all proposed non-invasive side-channel methods suffer from noise and, therefore, have low confidence. Moreover, they require activating the tampered part of the circuit (e.g., the Trojan trigger) to compare and detect the modifications. In this work, we introduce a non-invasive post-silicon tamper detection technique applicable to different classes of tamper events at the chip level without requiring the activation of the malicious circuit. Our method relies on the fact that physical modifications (regardless of their physical, activation, or action characteristics) alter the impedance of the chip. Hence, characterizing the impedance can lead to the detection of the tamper events. To sense the changes in the impedance, we deploy known RF tools, namely, scattering parameters, in which we inject sine wave signals with high frequencies to the power distribution network (PDN) of the system and measure the “echo” of the signal. The reflected signals in various frequency bands reveal different tamper events based on their impact size on the die. To validate our claims, we performed measurements on several proof-ofconcept tampered hardware implementations realized on FPGAs manufactured with a 28 nm technology. We further show that deploying the Dynamic Time Warping (DTW) distance can distinguish between tamper events and noise resulting from manufacturing process variation of different chips/boards. Based on the acquired results, we demonstrate that stealthy hardware Trojans, as well as sophisticated modifications of P&R, can be detected

Influence of polyaniline and cerium oxide nanoparticles on the corrosion protection properties of alkyd coating

A study of the anticorrosive properties of an alkyd coating loaded with polyaniline and cerium oxide (CeO2) nanoparticles is presented in this paper. Investigated by means of Electrochemical Impedance Spectroscopy and accelerated salt spray test, the blank alkyd coating has been loaded with PAni, ceria nanoparticles and the combination of both with 1.0 wt.% content. Through the monitoring of open circuit potential, an ennoblement effect was detected for the systems in the presence of a mild solution. Moreover, EIS evolution of the alkyd containing polyaniline revealed a stable performance of the system in the presence of sulphate solution, whereas for those containing ceria nanoparticles a considerable raise in the |Z|0.015 Hz, from 107 to 108 Ω cm2 in the course of 24 h of immersion, an increasing trend of the charge transfer resistance during the equivalent period of exposure was observed. Furthermore, the anticorrosive contribution given by the ceria nanoparticlesis supported by the accelerated salt spray test which revealed lower delamination rates. In the case of the alkyd loaded with polyaniline and ceria nanoparticles simultaneously the evidences are less perceived by means of electrochemical analysis, however, from salt spray tests it can be seen that the influence of the mixture is promising at a certain extent.</p