An open label randomized controlled trial of tamoxifen combined with amphotericin B and fluconazole for cryptococcal meningitis

Background: Cryptococcal meningitis has high mortality. Flucytosine is a key treatment but is expensive and rarely available. The anti-cancer agent tamoxifen has synergistic anti-cryptococcal activity with amphotericin in vitro. It is off-patent, cheap, and widely available. We performed a trial to determine its therapeutic potential. Methods:Open label randomized controlled trial. Participants received standard care - amphotericin combined with fluconazole for the first two weeks - or standard care plus tamoxifen 300mg/day. The primary end point was Early Fungicidal Activity (EFA) - the rate of yeast clearance from cerebrospinal fluid (CSF). Trial registration https://clinicaltrials.gov/ct2/show/NCT03112031 . Results: 50 patients were enrolled, (median age 34 years, 35 male). Tamoxifen had no effect on EFA (- 0.48log10 colony-forming units/mL/CSF control arm versus -0.49 tamoxifen arm, difference - 0.005log10CFU/ml/day, 95%CI: -0.16, 0.15, P=0.95). Tamoxifen caused QTc prolongation. Conclusion: High dose tamoxifen does not increase the clearance rate of Cryptococcus from CSF. Novel, affordable therapies are needed. Funding:The trial was funded through the Wellcome Trust Asia Programme Vietnam Core Grant 106680 and a Wellcome Trust Intermediate Fellowship to JND grant number WT097147MA

Geoeconomic variations in epidemiology, ventilation management, and outcomes in invasively ventilated intensive care unit patients without acute respiratory distress syndrome: a pooled analysis of four observational studies

Background: Geoeconomic variations in epidemiology, the practice of ventilation, and outcome in invasively ventilated intensive care unit (ICU) patients without acute respiratory distress syndrome (ARDS) remain unexplored. In this analysis we aim to address these gaps using individual patient data of four large observational studies. Methods: In this pooled analysis we harmonised individual patient data from the ERICC, LUNG SAFE, PRoVENT, and PRoVENT-iMiC prospective observational studies, which were conducted from June, 2011, to December, 2018, in 534 ICUs in 54 countries. We used the 2016 World Bank classification to define two geoeconomic regions: middle-income countries (MICs) and high-income countries (HICs). ARDS was defined according to the Berlin criteria. Descriptive statistics were used to compare patients in MICs versus HICs. The primary outcome was the use of low tidal volume ventilation (LTVV) for the first 3 days of mechanical ventilation. Secondary outcomes were key ventilation parameters (tidal volume size, positive end-expiratory pressure, fraction of inspired oxygen, peak pressure, plateau pressure, driving pressure, and respiratory rate), patient characteristics, the risk for and actual development of acute respiratory distress syndrome after the first day of ventilation, duration of ventilation, ICU length of stay, and ICU mortality. Findings: Of the 7608 patients included in the original studies, this analysis included 3852 patients without ARDS, of whom 2345 were from MICs and 1507 were from HICs. Patients in MICs were younger, shorter and with a slightly lower body-mass index, more often had diabetes and active cancer, but less often chronic obstructive pulmonary disease and heart failure than patients from HICs. Sequential organ failure assessment scores were similar in MICs and HICs. Use of LTVV in MICs and HICs was comparable (42\ub74% vs 44\ub72%; absolute difference \u20131\ub769 [\u20139\ub758 to 6\ub711] p=0\ub767; data available in 3174 [82%] of 3852 patients). The median applied positive end expiratory pressure was lower in MICs than in HICs (5 [IQR 5\u20138] vs 6 [5\u20138] cm H2O; p=0\ub70011). ICU mortality was higher in MICs than in HICs (30\ub75% vs 19\ub79%; p=0\ub70004; adjusted effect 16\ub741% [95% CI 9\ub752\u201323\ub752]; p<0\ub70001) and was inversely associated with gross domestic product (adjusted odds ratio for a US$10 000 increase per capita 0\ub780 [95% CI 0\ub775\u20130\ub786]; p<0\ub70001). Interpretation: Despite similar disease severity and ventilation management, ICU mortality in patients without ARDS is higher in MICs than in HICs, with a strong association with country-level economic status. Funding: No funding

Safety and efficacy of fluoxetine on functional outcome after acute stroke (AFFINITY): a randomised, double-blind, placebo-controlled trial

Background Trials of fluoxetine for recovery after stroke report conflicting results. The Assessment oF FluoxetINe In sTroke recoverY (AFFINITY) trial aimed to show if daily oral fluoxetine for 6 months after stroke improves functional outcome in an ethnically diverse population. Methods AFFINITY was a randomised, parallel-group, double-blind, placebo-controlled trial done in 43 hospital stroke units in Australia (n=29), New Zealand (four), and Vietnam (ten). Eligible patients were adults (aged ≥18 years) with a clinical diagnosis of acute stroke in the previous 2–15 days, brain imaging consistent with ischaemic or haemorrhagic stroke, and a persisting neurological deficit that produced a modified Rankin Scale (mRS) score of 1 or more. Patients were randomly assigned 1:1 via a web-based system using a minimisation algorithm to once daily, oral fluoxetine 20 mg capsules or matching placebo for 6 months. Patients, carers, investigators, and outcome assessors were masked to the treatment allocation. The primary outcome was functional status, measured by the mRS, at 6 months. The primary analysis was an ordinal logistic regression of the mRS at 6 months, adjusted for minimisation variables. Primary and safety analyses were done according to the patient's treatment allocation. The trial is registered with the Australian New Zealand Clinical Trials Registry, ACTRN12611000774921. Findings Between Jan 11, 2013, and June 30, 2019, 1280 patients were recruited in Australia (n=532), New Zealand (n=42), and Vietnam (n=706), of whom 642 were randomly assigned to fluoxetine and 638 were randomly assigned to placebo. Mean duration of trial treatment was 167 days (SD 48·1). At 6 months, mRS data were available in 624 (97%) patients in the fluoxetine group and 632 (99%) in the placebo group. The distribution of mRS categories was similar in the fluoxetine and placebo groups (adjusted common odds ratio 0·94, 95% CI 0·76–1·15; p=0·53). Compared with patients in the placebo group, patients in the fluoxetine group had more falls (20 [3%] vs seven [1%]; p=0·018), bone fractures (19 [3%] vs six [1%]; p=0·014), and epileptic seizures (ten [2%] vs two [<1%]; p=0·038) at 6 months. Interpretation Oral fluoxetine 20 mg daily for 6 months after acute stroke did not improve functional outcome and increased the risk of falls, bone fractures, and epileptic seizures. These results do not support the use of fluoxetine to improve functional outcome after stroke

Efficient Integrated Circuits for Wideband Wireless Transceivers

The proliferation of portable communication devices combined with the relentless demand for higher data rates has spurred the development of wireless communication standards which can support wide signal bandwidths. Benefits of the complementary metal oxide semiconductor (CMOS) process such as high device speeds and low manufacturing cost have rendered it the technology of choice for implementing wideband wireless transceiver integrated circuits (ICs). This dissertation addresses the key challenges encountered in the design of wideband wireless transceiver ICs. It is divided into two parts. Part I describes the design of crucial circuit blocks such as a highly selective wideband radio frequency (RF) front-end and an on-chip test module which are typically found in wireless receivers. The design of high-speed, capacitive DACs for wireless transmitters is included in Part II. The first work in Part I is the design and implementation of a wideband RF frontend in 65-nm CMOS. To achieve blocker rejection comparable to surface-acousticwave (SAW) filters, the highly selective and tunable RF receiver utilizes impedance transformation filtering along with a two-stage architecture. It is well known that the low-noise amplifier (LNA) which forms the first front-end stage largely decides the receiver performance in terms of noise figure (NF) and linearity (IIP3/P1dB). The proposed LNA uses double cross-coupling technique to reduce NF while complementary derivative superposition (DS) and resistive feedback are employed to achieve high linearity. The resistive feedback also enhances input matching. In measurements, the front-end achieves performance comparable to SAW filters with blocker rejection greater than 38 dB, NF 3.2–5.2 dB, out-of-band IIP3 &gt; +17 dBm and blocker P1dB &gt; +5 dBm over a frequency range of 0.5–3 GHz. The second work in Part I is the design of an RF amplitude detector for on-chip test. As the complexity of RF ICs continues to grow, the task of testing and debugging them becomes increasingly challenging. The degradation in performance or the drift from the optimal operation points may cause systems to fail. To prevent this effect and ensure acceptable performance in the presence of process, voltage and temperature variations (PVT), test and calibration of the RF ICs become indispensable. A wideband, high dynamic range RF amplitude detector design aimed at on-chip test is proposed. Gain-boosting and sub-ranging techniques are applied to the detection circuit to increase the gain over the full range of input amplitudes without compromising the input impedance. A technique suitable for on-chip third/second-order intercept  point (IP3/IP2) test by embedded RF detectors is also introduced. Part II comprises the design and analysis of high-speed switched-capacitor (SC) DACs for 60-GHz radio transmitters. The digital-to-analog converter (DAC) is one of the fundamental building blocks of transmitters. SC DACs offer several advantages over the current-steering DAC architecture. Specifically, lower capacitor mismatch helps the SC DAC to achieve higher linearity. The switches in the SC DAC are realized by MOS transistors in the triode region which substantially relaxes the voltage headroom requirement. Consequently, SC DACs can be implemented using lower supply voltages in advanced CMOS process nodes compared to their currentsteering counterparts. The first work in Part II analyzes the factors limiting the performance of capacitive pipeline DACs. It is shown that the DAC performance is  limited mainly by the clock feed-through and settling effects in the SC  arrays while the impact of capacitor mismatch and kT/C noise are found to be negligible. Based on this analysis, the second work in Part II proposes the split-segmented SC array DAC to overcome the clock feed-through problem since this topology eliminates pipelined charge propagation. Implemented in 65-nm CMOS, the 12-bit SC DAC achieves a Spurious Free Dynamic Range (SFDR) greater than 44 dB within the input signal bandwidth (BW) of 1 GHz with on-chip memory embedded for digital data generation. Power dissipation is 50 mW from 1.2 V supply. Similar performance is achieved with a lower supply voltage (0.9 V) which shows the scalability of the SC DAC for more advanced CMOS technologies. Furthermore, the proposed SC DAC satisfies the spectral mask of the IEEE 802.11ad WiGig standard with a second-order reconstruction filter and hence it can be used for the 60-GHz radio baseband

Design and analysis of high-speed split-segmented switched-capacitor DACs

In order to achieve high speed and high resolution for switched-capacitor (SC) digital-to-analog converters (DACs), an architecture of split-segmented SC DAC is proposed. The detailed design considerations of kT/C noise, capacitor mismatch, settling time and simultaneous switching noise are mathematically analyzed and modelled. The design area W–Cu is defined based on that analysis. It is used not only to identify the maximum speed and resolution but also to find the design point (W, Cu) for certain speed and resolution of SC DAC topology. The segmentation effects are also considered. An implementation example of this type of DACs is a 12-bit 6-6 split-segmented SC DAC designed in 65 nm CMOS. The linear open-loop output driver utilizing derivation superposition technique for nonlinear cancellation is used to drive off-chip load for the SC array without compromising its performance. The measured results show that the SC DAC achieves a 44 dB spurious free dynamic range within a 1 GHz bandwidth of input signal at 5 GS/s while consuming 50 mW from 1 V digital and 1.2 V analog supplies. The overall performance that was achieved from measurement is poorer than expected due to lower power supply rejection ratio in fabricated chip. This DAC can be used in transmitter baseband for wideband wireless communications.Funding agencies: Swedish Foundation for Strategic Research</p

Design and Analysis of High Speed Capacitive Pipeline DACs

Design of a high speed capacitive digital-to-analog converter (SC DAC) is presented for 65 nm CMOS technology. SC pipeline architecture is used followed by an output driver. For GHz frequency operation with output voltage swing suitable for wireless applications (300 mVpp) the DAC performance is shown to be limited by the capacitor array imperfections. While it is possible to design a highly linear output driver with HD3 &lt; -70 dB and HD2 &lt; -90 dB over 0.55 GHz band as we show, the maximum SFDR of the SC DAC is 45 dB with 8-bit resolution and Nyquist sampling of 3 GHz. The analysis shows the DAC performance is determined by the clock feed-through and settling effects in the SC array and not by the capacitor mismatch or kT/C noise, which appear negligible in this application. The capacitor array is designed based on the DAC design area defined in terms of the switch size and unit capacitance value. A tradeoff between the DAC bandwidth and resolution accompanied by SFDR is demonstrated. The high linearity of the output driver is attained by a combination of two techniques, the derivative superposition (DS) and resistive source degeneration. In simulations the complete Nyquist-rate DAC achieves SFDR of 45 dB with 8-bit resolution for signal bandwidth 1.36 GHz. With 6-bit and 5.5 GHz bandwidth 33 dB SFDR is attained. The total power consumption of the SC DAC is 90 mW with 1.2 V supply and clock frequency of 3 GHz

Analysis and design of low noise transconductance amplifier for selective receiver front-end

Analysis and design of a low-noise transconductance amplifier (LNTA) aimed at selective current-mode (SAW-less) wideband receiver front-end is presented. The proposed LNTA uses double cross-coupling technique to reduce noise figure (NF), complementary derivative superposition, and resistive feedback to achieve high linearity and enhance input matching. The analysis of both NF and IIP3 using Volterra series is described in detail and verified by SpectreRF (A (R)) circuit simulation showing NF less than 2 dB and IIP3 = 18 dBm at 3 GHz. The amplifier performance is demonstrated in a two-stage highly selective receiver front-end implemented in 65 nm CMOS technology. In measurements the front-end achieves blocker rejection competitive to SAW filters with noise figure 3.2-5.2 dB, out of band IIP3 greater than+17 dBm and blocker P-1dB greater than+5 dBm over frequency range of 0.5-3 GHz