Reduction techniques of the back gate effect in the SOI Pixel Detector

We have fabricated monolithic pixel sensors in 0.2 μm Silicon-On-Insulator (SOI) CMOS technology, consisting of a thick sensor layer and a thin circuit layer with an insulating buried-oxide, which has many advantages. However, it has been found that the applied electric field in the sensor layer also affects the transistor operation in the adjacent circuit layer. This limits the applicable sensor bias well below the full depletion voltage. To overcome this, we performed a TCAD simulation and added an additional p-well (buried pwell) in the SOI process. Designs and preliminary results are presented

Diffusion of hydrogen in crystalline silicon

The coefficient of diffusion of hydrogen in crystalline silicon is calculated using tight-binding molecular dynamics. Our results are in good quantitative agreement with an earlier study by Panzarini and Colombo [Phys. Rev. Lett. 73, 1636 (1994)]. However, while our calculations indicate that long jumps dominate over single hops at high temperatures, no abrupt change in the diffusion coefficient can be observed with decreasing temperature. The (classical) Arrhenius diffusion parameters, as a consequence, should extrapolate to low temperatures.Comment: 4 pages, including 5 postscript figures; submitted to Phys. Rev. B Brief Repor

Changing shapes in the nanoworld

What are the mechanisms leading to the shape relaxation of three dimensional crystallites ? Kinetic Monte Carlo simulations of fcc clusters show that the usual theories of equilibration, via atomic surface diffusion driven by curvature, are verified only at high temperatures. Below the roughening temperature, the relaxation is much slower, kinetics being governed by the nucleation of a critical germ on a facet. We show that the energy barrier for this step linearly increases with the size of the crystallite, leading to an exponential dependence of the relaxation time.Comment: 4 pages, 5 figures. Accepted by Phys Rev Let

System Test of the ATLAS Muon Spectrometer in the H8 Beam at the CERN SPS

An extensive system test of the ATLAS muon spectrometer has been performed in the H8 beam line at the CERN SPS during the last four years. This spectrometer will use pressurized Monitored Drift Tube (MDT) chambers and Cathode Strip Chambers (CSC) for precision tracking, Resistive Plate Chambers (RPCs) for triggering in the barrel and Thin Gap Chambers (TGCs) for triggering in the end-cap region. The test set-up emulates one projective tower of the barrel (six MDT chambers and six RPCs) and one end-cap octant (six MDT chambers, A CSC and three TGCs). The barrel and end-cap stands have also been equipped with optical alignment systems, aiming at a relative positioning of the precision chambers in each tower to 30-40 micrometers. In addition to the performance of the detectors and the alignment scheme, many other systems aspects of the ATLAS muon spectrometer have been tested and validated with this setup, such as the mechanical detector integration and installation, the detector control system, the data acquisition, high level trigger software and off-line event reconstruction. Measurements with muon energies ranging from 20 to 300 GeV have allowed measuring the trigger and tracking performance of this set-up, in a configuration very similar to the final spectrometer. A special bunched muon beam with 25 ns bunch spacing, emulating the LHC bunch structure, has been used to study the timing resolution and bunch identification performance of the trigger chambers. The ATLAS first-level trigger chain has been operated with muon trigger signals for the first time

Sector logic implementation for the ATLAS endcap level-1 muon trigger

We present development of the Sector Logic for the ATLAS endcap Level-1 (LVL1) muon trigger. The muon tracks from the interaction point (IP) are bent by the magnetic fields induced by the ATLAS toroidal magnets. The Sector Logic reconstructs three dimensional muon tracks with six levels of transverse momentum (pT) by combining two sets (R-Z and φ-Z) of information from the Thin Gap Chamber (TGC) detectors. Then, it selects two highest pT tracks in each trigger sector. The Sector Logic module is designed in pipelined structure to achieve no-dead-time operation and shorter latency. Look-Up-Tables (LUTs) are used so that any pT threshold level can be set. To achieve these, we adopted SRAM embedded type FPGA devices. The design and its performance are given in this presentation