We have developed a silicon pixel detector to enhance the physics
capabilities of the PHENIX experiment. This detector, consisting of two layers
of sensors, will be installed around the beam pipe at the collision point and
covers a pseudo-rapidity of | \eta | < 1.2 and an azimuth angle of | \phi | ~
2{\pi}. The detector uses 200 um thick silicon sensors and readout chips
developed for the ALICE experiment. In order to meet the PHENIX DAQ readout
requirements, it is necessary to read out 4 readout chips in parallel. The
physics goals of PHENIX require that radiation thickness of the detector be
minimized. To meet these criteria, the detector has been designed and
developed. In this paper, we report the current status of the development,
especially the development of the low-mass readout bus and the front-end
readout electronics.Comment: 9 pages, 8 figures and 1 table in DOCX (Word 2007); PIXEL 2008
  workshop proceedings, will be published in the Proceedings Section of
  JINST(Journal of Instrumentation

A Taketani

A. Kluge

C Pancake

E Atomssa

E J Mannel

E Shafto

F Gastaldi

H En'yo

H Ohnishi

K Fujiwara

K Kurita

M Kasai

M Kurosawa

M Sekimoto

M. Baker .

N Apadula

O Drapier

R Granier de Cassagnac

R Ichimiya

R Pak

R. Nouicer

S Chollet

W Sondheim

Y Akiba

Y Onuki

English

arXiv

Ichimiya, R

Apadula, N

Akiba, Y

Atomssa, E

Chollet, S

Drapier, O

En'yo, H

Fujiwara, K

Gastaldi, F

GranierdeCassagnac, R

Kasai, M

Kurita, K

Kurosawa, M

Mannel, E J

Ohnishi, H

Onuki, Y

Pak, R

Pancake, C

Sekimoto, M

Shafto, E

Sondheim, W

Taketani, A

CERN Document Server

2009 JINST 4 P05001PUBLISHED BY IOP PUBLISHING FOR SISSARECEIVED: December 15, 2008REVISED: March 19, 2009ACCEPTED: March 27, 2009PUBLISHED: May 5, 2009PIXEL 2008 INTERNATIONAL WORKSHOPFERMILAB, BATAVIA, IL, U.S.A.23–26 SEPTEMBER 2008Status and overview of development of the siliconpixel detector for the PHENIX experiment at the BNLRHICR. Ichimiya,a,1 N. Apadula,b Y. Akiba,a E. Atomssa,c S. Chollet,c O. Drapier,cH. En’yo,a K. Fujiwara,a F. Gastaldi,c R. Granier de Cassagnac,c M. Kasai,dK. Kurita,d M. Kurosawa,a E.J. Mannel,e H. Ohnishi,a Y. Onuki,a R. Pak, fC. Pancake,b M. Sekimoto,g E. Shafto,b W. Sondheimh and A. TaketaniaaRIKEN Nishina Center for Accelerator-Based Science,2-1, Hirosawa, Wako, Saitama 351-0198, JapanbStony Brook University,Stony Brook, NY 11794, U.S.A.cLLR, Ecole Polytechnique, CNRS-IN2P3,91128 PALAISEAU Cedex, FrancedRikkyo University,3-34-1, Nishi-Ikebukuro, Toshima-ku, Tokyo, JapaneColumbia University,New York, NY 10027, U.S.A.fBrookhaven National Laboratory,Upton, NY 11973, U.S.A.gHigh Energy Accelerator Research Organization,1-1, Oho, Tsukuba, Ibaraki 305-0801, JapanhLos Alamos National Laboratory,Los Alamos, NM 87545, U.S.A.E-mail: ryo@riken.jpABSTRACT: We have developed a silicon pixel detector to enhance the physics capabilities of thePHENIX experiment. This detector, consisting of two layers of sensors, will be installed aroundthe beam pipe at the collision point and covers a pseudo-rapidity of |η |< 1.2 and an azimuth angleof |φ | ∼ 2pi . The detector uses 200 µm thick silicon sensors and readout chips developed for the1Corresponding author.c© 2009 IOP Publishing Ltd and SISSA doi:10.1088/1748-0221/4/05/P050012009 JINST 4 P05001ALICE experiment. In order to meet the PHENIX DAQ readout requirements, it is necessary toread out 4 readout chips in parallel. The physics goals of PHENIX require that radiation thicknessof the detector be minimized. To meet these criteria, the detector has been designed and developed.In this paper, we report the current status of the development, especially the development of thelow-mass readout bus and the front-end readout electronics.KEYWORDS: Particle tracking detectors; Instrumentation and methods for heavy-ion reactions andfission studiesARXIV EPRINT: 0812.283412009 JINST 4 P05001Contents1 Introduction 12 Silicon pixel detector 12.1 Pixel Readout Bus 32.2 SPIRO module 43 Beam test 54 Summary 71 IntroductionThe Pioneering High Energy Nuclear Interaction eXperiment (PHENIX) at the Relativistic HeavyIon Collider (RHIC) at the Brookhaven National Laboratory (BNL), which has been exploring bothspin structure of the nucleon utilizing polarized proton-proton collisions and characteristics of theQuark Gluon Plasma created in heavy ion collisions, is being upgraded with a silicon vertex tracker(VTX) to gain precise information near the collision point. The primary purpose of the VTX is tocarry out precise measurements of heavy-quark production (charm and beauty) in A + A, p(d) +A and polarized p+ p collisions. These are essential measurements for future heavy-ion and spin-physics programs at RHIC. The VTX must be able to distinguish heavy quarks from light quarksby detecting a displaced vertex due to the longer lifetime of heavy quarks, whose cτ range from100 µm (charm) to 400 µm (bottom). In addition, the precise tracking capabilities in high chargedparticle densities dN / dη ∼ 700 (at η = 0), of the VTX will provide significant improvements toother physics measurements.2 Silicon pixel detectorThe VTX detector consists of two inner layers of silicon pixel detectors with radii of 25 and 50 mmand two outer layers of silicon strip detectors with radii of 100 and 140 mm, as shown in figure 1.The detector covers a pseudo-rapidity of |η | < 1.2 and ∆φ ∼ 2pi . The silicon strip detector isa single-sided, DC-coupled, two-dimensional silicon detector, which was developed at BNL [1].The specifications of the VTX pixel detectors are summarized in table 1 [2]–[3].The technology used for the two inner layers of pixel detectors is based on the ALICE ITSdetector developed at CERN. A 200-µm-thick silicon sensor fabricated by CANBERRA is a mod-ified version of the ALICE sensor [4], that holds 4 (readout chip) × 32 (column) × 256 (row)pixels, each with an active area of 50 × 425 µm2. We used the same readout chip [5] as ALICEITS uses. The sensor is bump bonded to four matching readout chips, each having a thickness of– 1 –2009 JINST 4 P05001Figure 1. Three-dimensional drawing of the VTX with the beam pipe (Left). The VTX sensor consists oftwo inner layers of silicon pixel detectors (25 mm, 50 mm) and two outer layers of silicon strip detectors(100 mm, 140 mm). The five pixel ladders with the both sides of the bus extenders and the SPIRO modulesare displayed (Right). The readout bus is located at the inner barrel region and the SPIRO modules arelocated at the outer region.Table 1. Main parameters of silicon pixel layers.VTX Layer R1 R2R (mm) 25 50∆z (mm) 218Geometrical dimensions Area (mm2) 28,000 56,000Number of Ladders 10 20Readout channels 1,310,720 2,620,440Sensor hybridSensor size 128 mm × 13.6 mmALICE1/LHCb chips 15.6 mm × 13.5 mm (× 4)Pixel size 50 µm × 425 µmReadout chips 160 320Radiation length per layer (X/X0)Sensor 0.21%Readout 0.16%Bus 0.22%Support and cooling 0.67%Total 1.26%150 µm. Each readout chip has 32 × 256 amplifier-discriminators for individual channels. Thedata is read out in a pipeline fashion. Four readout chips mounted on a sensor using bump-bondingtechnology form a sensor hybrid. Two sensor hybrids are glued to a pixel readout bus made of Cu-Al-Polyimide, which is supported by a carbon fiber structure. The pixel readout bus is connected to– 2 –2009 JINST 4 P05001Figure 2. A half ladder with bus extender and SPIRO module. The SPIRO module is located at the outerregion, and the bus extender connects the pixel readout bus to the SPIRO module, as shown in figure 1.the Silicon Pixel Interface Read-Out (SPIRO) module via a bus extender, which provides all servicevoltages, control and timing signals, and reads out the pixel data. The SPIRO module transmits thedata to the Front End Module (FEM) via serial optical links. The FEM interprets and sends thedata to the PHENIX data acquisition system (DAQ). The Bus extender is a Flexible Printed Circuitboard (FPC) which feeds the data from the readout bus in the inner barrel to the SPIRO module inthe outer region (See figure 1(Right)).A pixel readout bus, a bus extender, and one SPIRO module form a half ladder, the basicbuilding unit of the pixel detector. Two half ladders form a full ladder, which spans approximately22 cm in the beam direction. Ten ladders in the first layer and 20 ladders in the second layer togethercover almost the entire azimuthally angle. The combined materials of silicon sensor, readout chip,readout bus, and mechanical support including the cooling structure add up to about 1.26% of aradiation length for one pixel layer.2.1 Pixel Readout BusTo meet the readout speed requirements of PHENIX, we adopted parallel readout scheme (seefigure 5 and section 2.2). Therefore the pixel readout bus is required to have 188 signal lines,250mm long, within a 13.9mm width. Moreover, in order to minimize the multiple scattering andphoton conversion in the structure, the readout bus must be as thin in material as possible. Tosatisfy these criteria, we selected the FPC technology to fabricate the bus. The development of thepixel readout bus was challenging business for fabricating a high density (60 µm pitch) and longlength (250 mm) bus.We have developed a new copper-aluminium-polyimide FPC that has 188 signal lines with0.22% X0 in radiation length. The bus has four copper signal layers of 3 µm thickness and twoaluminum power layers of 50 µm thickness. For the signal layers, we used 30 µm line width andspacing. In order to achieve a high yield in the manufacturing stage, we had to optimize the wiringpattern, through hole via plating and fabrication process.We have done a signal transmission simulation of the pixel readout bus using the HSPICEsimulator to evaluate the performance of the pixel bus for resistance, transmitted waveforms, andcross talks on the neighbouring lines [6]. A transmission line model with actual cross section andlength of line was used for the simulation input. In addition, realistic models of the transmitterand receiver circuits were used. The results of the simulation were compared to the propagationcharacteristics, which were measured using a prototype half ladder. The simulation results andmeasured values were in good agreement and the crosstalk level was sufficiently low for the stable– 3 –2009 JINST 4 P05001Figure 3. Photograph of pre-production pixel readout bus. This bus is fabricated using fine-pitch (60 µm)FPC technology, and it has a length of 250 mm and a width of 13.9 mm.Figure 4. Block diagram of SPIRO module (Left); photograph of SPIRO module (Right).operation of the half ladder. We tuned the pull-up resistor values using this simulation methodand concluded a 220 Ω termination resistor gives the best propagation characteristics for the halfladder.2.2 SPIRO moduleAs mentioned above, the SPIRO module is the frontend electronics for the half-ladders. It consistsof two Digital Pilot ASICs, two Analogue Pilot ASICs, a control FPGA, two Gigabit Optical Link(GOL) high-speed serializer ASICs, which were developed at CERN and three optical transceiversas shown in figure 4. Figure 5 shows the readout diagram from the pixel bus through the SPIROmodule to the PHENIX DAQ.The SPIRO module performs the following functions:• Transmitting control signals to the half-ladder.• Multiplexing data from the half-ladder and transmitting them to the FEM via optical links.• Providing slow control of the pixel readout chips and the SPIRO module itself.The core components of the SPIRO module are the Digital Pilot ASICs. Each of the two pixelreadout chip pairs presents 256× 2 sequential words of data to a 32-bit bus synchronously at a beamcollision clock frequency (BCO) of 9.4 MHz. To meet the readout speed requirements of PHENIX,four readout chips are read out in parallel. To optimize the readout speed and space factor, thePHENIX Digital Pilot ASIC with twice the number of input channels was developed using the samedesign rules and radiation tolerant technology as the original ALICE Digital Pilot ASIC [7]. ThePHENIX Digital Pilot ASIC with 2×32 inputs can simultaneously read two 32-bit words from two– 4 –2009 JINST 4 P05001Figure 5. Readout diagram from the pixel readout bus through the SPIRO module to the PHENIX DAQ.pixel readout chips. Each 32-bit input handles the output from a pair of chips, which represents 512sequential words of pixel data. Each of the two Analogue Pilot ASICs provides several referencevoltages using on-chip Digital-to-Analogue Converters and monitors the voltages and currents offour pixel readout chips using an on-chip Analogue-to-Digital Converter. We use the AnaloguePilot ASICs without any modifications. The FPGA transfers the data from the PHENIX globalclock (4 × BCO) domain to a low-jitter local clock (40 MHz) domain using an on-chip First-InFirst-Out memory. Two GOL ASICs serialize the 32-bit-wide data into a 1.6 Gbps serial string.3 Beam testA full chain test was conducted using a telescope with three layers of pre-production pixel ladders,bus extenders, SPIRO modules, a FEM and a PHENIX DAQ system to demonstrate the perfor-mance of the system. This test was conducted using a 120 GeV proton beam at the MTEST Facilityat Fermi National Accelerator Laboratory (FNAL) in August 2008, FNAL T-984.Figure 6 shows the beam test setup. A strip detector is also installed to the setup and the dataare taken independently. Three pixel half ladders are stacked along the beam direction. Each halfladder is connected to a SPIRO module. All the SPIRO modules are controlled by a single FEM viaoptical fibres. The trigger required all 3 layers having a hit in coincidence with scintillation triggercounters, which were located upstream and downstream of the telescope. When the FEM receivedthe trigger signal, it transmits a level-1 trigger to all the half ladders. The pixel hit information isthen collected by the PHENIX DAQ system through the SPIRO modules and the FEM.All systems were operated as designed and the hit data were recorded by the PHENIX DAQsystem at a trigger rate of typically 34–38Hz. This trigger rate is considerably lower than that of theactual PHENIX (up to 10 kHz) and the number of input channels to the DAQ system is very small.Otherwise all other experimental conditions are identical to those of the PHENIX experiment. Atypical beam event is shown in figure 7. The three figures on the left show the hit positions on eachlayer after clustering of hits. The figure on the right represents the three-dimensional hit positionsand the reconstructed track after geometrical alignment was performed.– 5 –2009 JINST 4 P05001Figure 6. Setup of beam test. The proton beam passes through each sensor hybrid from top to bottom. Threepixel half ladder layers are stacked along the beam direction.Figure 7. Hit positions at each pixel layer after clustering of consecutive hits (Left) and three-dimensionalhit positions and reconstructed track (Right).Figure 8 shows the residual distribution of the first layer (Layer 1 in figure 7) after geometricalalignment. The pixel size is 50 µm × 425 µm. The z direction is along the 425-µm side of thepixel, and the φ direction is along the 50-µm side of the pixel. The pixel sensor is expected to haveresolutions of 123 µm (=425/√12) and 14 µm (=50/√12) in the z and φ directions, respectively.– 6 –2009 JINST 4 P05001Figure 8. Residual distributions of Layer 1 along z and φ directions. Pixel size is 50 µm × 425 µm; zdirection is along the 425-µm side of the pixel and φ direction is along the 50-µm side of the pixel.We determined the intrinsic position resolution of the sensor hybrid to be 109 ± 37 µm and 13± 5 µm in the z and φ directions, respectively. The error is the statistical error not including thesystematic error. They agreed with the expected values well.4 SummaryWe have developed a silicon pixel detector for the PHENIX upgrade, using a sensor and a readoutchip developed for the ALICE experiment at CERN. Based on the original ALICE pixel detectorsystem, we have developed the pixel readout bus, bus extender, SPIRO module, and FEM module.We have succeeded in developing a high-density (188 traces in a width of 13.9 mm) and thin(radiation length of 0.22% X0) pixel readout bus. A full chain test was conducted on the pixeldetector system using pre-production pixel ladders, frontend electronics, and the PHENIX DAQsystem at the MTest Facility at FNAL in August 2008, to demonstrate the system performance.AcknowledgmentsWe would like to thank everyone who helped us in this study, especially our collaborators in theCERN micro electronics group and the ALICE pixel detector group. We thank Mr. Bista Deepakand Mr. Jumpei Kanaya for their efforts on chip QA. We also wish to thank the staff of the FNALMTest Facility and Accelerator Division.References[1] R. Nouicer, Silicon Vertex Tracker for PHENIX Upgrade at RHIC: capabilities and DetectorTechnology, PoS(Vertex 2007)042 [arXiv:0801.2947].[2] M. Baker et al., Proposal for a Silicon Vertex Tracker (VTX) for the PHENIX Experiment, PhysicsDept. BNL, BNL-72204-2004 (2004).– 7 –2009 JINST 4 P05001[3] PHENIX collaboration, H. Ohnishi, The PHENIX vertex detector upgrade, Nucl. Instrum. Meth. A569 (2006) 33.[4] K. Wyllie et. al., Silicon detectors and electronics for pixel hybrid photon detectors, Nucl. Instrum.Meth. A 530 (2004) 82.[5] W. Snoeys et. al., Pixel readout electronics development for the ALICE pixel vertex and LHCb RICHdetector, Nucl. Instrum. Meth. A 465 (2000) 176.[6] K. Fujiwara et al., Fine pitch and low material readout bus for Silicon Pixel Detector in PHENIXVertex Tracker, IEEE Trans. Nucl. Sci. 56 (2007) 250.[7] A. Kluge, ALICE Silicon Pixel On Detector Pilot System OPS2003 — The missing manual, CERNInternal Note ALICE-INT-2004-030 (2005).– 8 –

Status and overview of development of the silicon pixel detector for the PHENIX experiment at the BNL RHIC

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Status and overview of development of the Silicon Pixel Detector for the
  PHENIX experiment at the BNL RHIC

Status and overview of development of the Silicon Pixel Detector for the PHENIX experiment at the BNL RHIC

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