HopliteBuf FPGA Network-on-Chip: Architecture and Analysis

We can prove occupancy bounds of stall-free FIFOs used in deflection-free, low-cost, and high-speed FPGA overlay Network-on-chips (NoCs). In our work, we build on top of the HopliteRT livelock-free overlay NoC with an FPGA-friendly 2D unidirectional torus topology to propose the novel HopliteBuf NoC. In our new NoC, we strategically introduce stall-free FIFOs in the network and support these FIFOs with static analysis based on network calculus to compute FIFO occupancy, latency, and bandwidth bounds. The microarchitecture of HopliteBuf combines the performance benefits of conventional buffered NoCs (high throughput, low latency) with the cost advantages of deflection-routed NoCs (low FPGA area, high clock frequencies). Specifically, we look at two design variants of the HopliteBuf NoC: (1) Single corner-turn FIFO (W to S), and (2) Dual corner-turn FIFO (W to S+N). The single corner-turn (W to S) design is simpler and only introduces a buffering requirement for packets changing dimension from X ring to the downhill Y ring (or West to South). The dual corner-turn variant requires two FIFOs for turning packets going downhill (W to S) as well as uphill (W to N). The dual corner-turn design overcomes the mathematical analysis challenges associated with single corner-turn designs for communication workloads with cyclic dependencies between flow traversal paths at the expense of small increase in resource cost. Essentially, we resolve an analysis challenge with extra hardware resources. Across a range of 100 synthetically-generated workloads on a 5 x 5 NoC, HopliteBuf outperforms HopliteRT by 1.2-2x in terms of latency, 10% in terms of injection rate, and 30-60% in terms of flowset feasibiliy. These advantages come at the cost of 3-4x higher FPGA resource requirement for buffers and muxes. Our analysis also deliver latency bounds that are not only better than HopliteRT in absolute terms but also tighter by 2-3x allowing us to provision less hardware to meet our specifications

Realization Of An 8-bit Pipelined Microprocessor in Verilog HDL

Pipelining is a technique of decomposing a sequential process into sub-operations, with each sub process being divided segment that operates concurrently with all other segments. A pipeline may be visualized as a collection of processing segments through which binary information flows. Each segment performs partial processing segments dictated by the way the task is partitioned. The result obtained in one segment is transferred to subsequent segments in each step. The final result is obtained after the data has passed through all segments.This paper develops a code for the implementation of an 8-Bit microprocessor which implements instruction pipelining. After synthesis, an FPGA realization may be obtained . Simulation using Xilinx and ModelSim also produces favourable results which showcase the speedup (in terms of time) to carry out a program as compared to a non-pipelined version of this microprocessor. Keywords:Pipelining, Segments,sysnthesis,realization,FPGA,microprocesso

Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube

Memories that exploit three-dimensional (3D)-stacking technology, which integrate memory and logic dies in a single stack, are becoming popular. These memories, such as Hybrid Memory Cube (HMC), utilize a network-on-chip (NoC) design for connecting their internal structural organizations. This novel usage of NoC, in addition to aiding processing-in-memory capabilities, enables numerous benefits such as high bandwidth and memory-level parallelism. However, the implications of NoCs on the characteristics of 3D-stacked memories in terms of memory access latency and bandwidth have not been fully explored. This paper addresses this knowledge gap by (i) characterizing an HMC prototype on the AC-510 accelerator board and revealing its access latency behaviors, and (ii) by investigating the implications of such behaviors on system and software designs

Design and Performance Evaluation of An Arduino Based Activity Tracker

Fitness band is an activity tracker that monitors the overall health of the wearer and helps us to predict the fitness plan to be followed on the basis of the number of footstep of the wearer over span of time. The band is connected to an android app where it can show user the various stats monitored by the band and the possible health plan which can be used to achieve the necessary health goals. The fitness band will also help in informing family members in case of some medical emergency

Understanding the design-space of sparse/dense multiphase GNN dataflows on spatial accelerators

Graph Neural Networks (GNNs) have garnered a lot of recent interest because of their success in learning representations from graph-structured data across several critical applications in cloud and HPC. Owing to their unique compute and memory characteristics that come from an interplay between dense and sparse phases of computations, the emergence of recon-figurable dataflow (aka spatial) accelerators offers promise for acceleration by mapping optimized dataflows (i.e., computation order and parallelism) for both phases. The goal of this work is to characterize and understand the design-space of dataflow choices for running GNNs on spatial accelerators in order for mappers or design-space exploration tools to optimize the dataflow based on the workload. Specifically, we propose a taxonomy to describe all possible choices for mapping the dense and sparse phases of GNN inference, spatially and temporally over a spatial accelerator, capturing both the intra-phase dataflow and the inter-phase (pipelined) dataflow. Using this taxonomy, we do deep-dives into the cost and benefits of several dataflows and perform case studies on implications of hardware parameters for dataflows and value of flexibility to support pipelined execution.Parts of this work were supported through a fellowship by NEC Laboratories Europe, Project grant PID2020-112827GB-I00 funded by MCIN/AEI/ 10.13039/501100011033, RTI2018-098156-B-C53 (MCIU/AEI/FEDER,UE) and grant 20749/FPI/18 from Fundación Séneca.Peer ReviewedPostprint (author's final draft

Unraveling Prostaglandin and NLRP3 Inflammasomemediated Pathways of Primary Dysmenorrhea and the Role of Mefenamic Acid and Its Combinations

Painful menstrual cramps during or around the time of the monthly cycle are known as dysmenorrhea. The estimated global prevalence in women of reproductive age ranges from 45% to 95%. It has a significant negative impact on regular activities and productivity at work. However, despite the severe consequences on quality of life, primary dysmenorrhea (PD) is underdiagnosed. Dysmenorrhea has complex pathogenesis. It involves the release of prostaglandins and activation of the nucleotide-binding oligomerization domain-like receptor protein 3 (NLRP3) inflammasome and also includes the involvement of other mediators such as bradykinin, histamine and acetylcholine. Even though nonsteroidal anti-inflammatory drugs (NSAIDs) remain the most common type of pain medication, the question of which one should be the most preferred is still open to debate. The current review examines the existing evidence for the pathogenesis of PD and makes evidence based and clinical experience based recommendations for the use of mefenamic acid and its combination in the treatment of dysmenorrhea. Mefenamic acid alleviates PD by inhibiting endometrial prostaglandin formation, restoring normal uterine activity, and reducing the inflammatory response by inhibiting the NLRP3 inflammasome and reducing the release of cytokines such as interleukin (IL)-1β. It is also known to have bradykinin antagonist activity. Dicyclomine has a dual action of blocking the muscarinic action of acetylcholine in postganglionic parasympathetic effect or regions and acting directly on uterine smooth muscle by blocking bradykinin and histamine receptors to relieve spasms. According to the experts, mefenamic acid and dicyclomine act synergistically by acting on the different pathways of dysmenorrhea by blocking multifactorial agents attributed to the cause of dysmenorrhea. Hence, the combination of mefenamic acid and dicyclomine should be the preferred treatment option for dysmenorrhea

Tropomyosin 1: multiple roles in the developing heart and in the formation of congenital heart defects

Tropomyosin 1 (TPM1) is an essential sarcomeric component, stabilising the thin filament and facilitating actin's interaction with myosin. A number of sarcomeric proteins, such as alpha myosin heavy chain, play crucial roles in cardiac development. Mutations in these genes have been linked to congenital heart defects (CHDs), occurring in approximately 1 in 145 live births. To date, TPM1 has not been associated with isolated CHDs. Analysis of 380 CHD cases revealed three novel mutations in the TPM1 gene; IVS1 + 2T > C, I130V, S229F and a polyadenylation signal site variant GATAAA/AATAAA. Analysis of IVS1 + 2T > C revealed aberrant pre-mRNA splicing. In addition, abnormal structural properties were found in hearts transfected with TPM1 carrying I130V and S229F mutations. Phenotypic analysis of TPM1 morpholino-treated embryos revealed roles for TPM1 in cardiac looping, atrial septation and ventricular trabeculae formation and increased apoptosis was seen within the heart. In addition, sarcomere assembly was affected and altered action potentials were exhibited. This study demonstrated that sarcomeric TPM1 plays vital roles in cardiogenesis and is a suitable candidate gene for screening individuals with isolated CHDs