Safe and Efficient Trajectory Optimization for Autonomous Vehicles using B-spline with Incremental Path Flattening

B-spline-based trajectory optimization is widely used for robot navigation due to its computational efficiency and convex-hull property (ensures dynamic feasibility), especially as quadrotors, which have circular body shapes (enable efficient movement) and freedom to move each axis (enables convex-hull property utilization). However, using the B-spline curve for trajectory optimization is challenging for autonomous vehicles (AVs) because of their vehicle kinodynamics (rectangular body shapes and constraints to move each axis). In this study, we propose a novel trajectory optimization approach for AVs to circumvent this difficulty using an incremental path flattening (IPF), a disc type swept volume (SV) estimation method, and kinodynamic feasibility constraints. IPF is a new method that can find a collision-free path for AVs by flattening path and reducing SV using iteratively increasing curvature penalty around vehicle collision points. Additionally, we develop a disc type SV estimation method to reduce SV over-approximation and enable AVs to pass through a narrow corridor efficiently. Furthermore, a clamped B-spline curvature constraint, which simplifies a B-spline curvature constraint, is added to dynamical feasibility constraints (e.g., velocity and acceleration) for obtaining the kinodynamic feasibility constraints. Our experimental results demonstrate that our method outperforms state-of-the-art baselines in various simulated environments. We also conducted a real-world experiment using an AV, and our results validate the simulated tracking performance of the proposed approach.Comment: 14 pages, 21 figures, 4 tables, 3 algorithm

Cyr61 Expression is associated with prognosis in patients with colorectal cancer

BACKGROUND: Cysteine-rich 61 (Cyr61), a member of the CCN protein family, possesses diverse functionality in cellular processes such as adhesion, migration, proliferation, and survival. Cyr61 can also function as an oncogene or a tumour suppressor, depending on the origin of the cancer. Only a few studies have reported Cyr61 expression in colorectal cancer. In this study, we assessed the Cyr61 expression in 251 colorectal cancers with clinical follow up. METHODS: We examined Cyr61 expression in 6 colorectal cancer cell lines (HT29, Colo205, Lovo, HCT116, SW480, SW620) and 20 sets of paired normal and colorectal cancer tissues by western blot. To validate the association of Cyr61 expression with clinicopathological parameters, we assessed Cyr61 expression using tissue microarray analysis of primary colorectal cancer by immunohistochemical analysis. RESULTS: We verified that all of the cancer cell lines expressed Cyr61; 2 cell lines (HT29 and Colo205) demonstrated Cyr61 expression to a slight extent, while 4 cell lines (Lovo, HCT116, SW480, SW620) demonstrated greater Cyr61 expression than HT29 and Colo205 cell lines. Among the 20 cases of paired normal and tumour tissues, greater Cyr61 expression was observed in 16 (80%) tumour tissues than in normal tissues. Furthermore, 157 out of 251 cases (62.5%) of colorectal cancer examined in this study displayed strong Cyr61 expression. Cyr61 expression was found to be associated with pN (p = 0.018). Moreover, Cyr61 expression was associated with statistically significant cancer-specific mortality (p = 0.029). The duration of survival was significantly lesser in patients with Cyr61 high expression than in patients with Cyr61 low expression (p = 0.001). These results suggest that Cyr61 expression plays several important roles in carcinogenesis and may also be a good prognostic marker for colorectal cancer. CONCLUSIONS: Our data confirmed that Cyr61 was expressed in colorectal cancers and the expression was correlated with worse prognosis of colorectal cancers

Development of simulation-based testing environment for safety-critical software

Recently, a software program has been used in nuclear power plants (NPPs) to digitalize many instrumentation and control systems. To guarantee NPP safety, the reliability of the software used in safety-critical instrumentation and control systems must be quantified and verified with proper test cases and test environment. In this study, a software testing method using a simulation-based software test bed is proposed. The test bed is developed by emulating the microprocessor architecture of the programmable logic controller used in NPP safety-critical applications and capturing its behavior at each machine instruction. The effectiveness of the proposed method is demonstrated via a case study. To represent the possible states of software input and the internal variables that contribute to generating a dedicated safety signal, the software test cases are developed in consideration of the digital characteristics of the target system and the plant dynamics. The method provides a practical way to conduct exhaustive software testing, which can prove the software to be error free and minimize the uncertainty in software reliability quantification. Compared with existing testing methods, it can effectively reduce the software testing effort by emulating the programmable logic controller behavior at the machine level

I2CRF: Incremental interconnect customization for embedded reconfigurable fabrics

Integrating coarse-grained reconfigurable architectures (CGRAs) into a System-on-a-Chip (SoC) presents many benefits as well as important challenges. One of the challenges is how to customize the architecture for the target applications efficiently and effectively without explicit design space exploration. In this paper we present a novel methodology for incremental interconnect customization of CGRAs that can suggest a new interconnection architecture that can maximize the performance for a given set of application kernels while minimizing the hardware cost. Applying the inexact graph matching analogy, we translate our problem into graph matching taking into account the cost of various graph edit operations, which we solve using the A* search algorithm with a heuristic tailored to our problem. Our experimental results demonstrate that our customization method can quickly find application-optimized interconnections that exhibit 70% higher performance on average compared to the base architecture, with relatively little hardware increase in interconnections and muxes

Architecture Customization of On-Chip Reconfigurable Accelerators

Integrating coarse-grained reconfigurable architectures (CGRAs) into a System-on-a-Chip (SoC) presents many benefits as well as important challenges. One of the challenges is how to customize the architecture for the target applications efficiently and effectively without performing explicit design space exploration. In this article we present a novel methodology for incremental interconnect customization of CGRAs that can suggest a new interconnection architecture which is able to maximize the performance for a given set of application kernels while minimizing the hardware cost. In our methodology, we translate the problem of interconnect customization into that of inexact graph matching, and we devised a heuristic for A search algorithm to efficiently solve the inexact graph matching problem. Our experimental results demonstrate that our customization method can quickly find application-optimized interconnections that exhibit 80% higher performance on average compared to the base architecture which has mesh interconnections, with little energy and hardware increase in interconnections and muxes.close0