Mixed signal design flow, a mixed signal PLL case study

Mixed-signal designs are becoming more and more complex every day. In order to adapt to the new market requirements, a formal process for design and verification of mixed signal systems i. e. top-down design and bottom-up verification methodology is required. This methodology has already been established for digital design. The goal of this research is to propose a new design methodology for mixed signal systems. In the first two chapters of this thesis, the need for a mixed signal design flow based on top-down design methodology will be discussed. The proposed design flow is based on behavioral modeling of the mixed signal system using one of the mixed signal behavioral modeling languages. These models can be used for design and verification through different steps of the design from system level modeling to final physical design. The other advantage of the proposed flow is analog and digital co-design. In the remaining chapters of this thesis, the proposed design flow was verified by designing an 800 MHz mixed signal PLL. The PLL uses a charge pump phase frequency detector, a single capacitor loop filter, and a feed forward error correction architecture using an active damping control circuit instead of passive resistor in loop filter. The design was done in 0. 18- µ m CMOS process technology

Analysis and design of an 80 Gbit/sec clock and data recovery prototype

La demande croissante de toujours plus de débit pour les télécommunications entraine une augmentation de la fréquence de fonctionnement des liaisons séries. Cette demande se retrouve aussi dans les systèmes embarqués du fait de l'augmentation des performances des composants et périphériques. Afin de s'assurer que le train de données est bien réceptionné, un circuit de restitution d'horloge et de données est placé avant tout traitement du coté du récepteur. Dans ce contexte, les activités de recherche présentées dans cette thèse se concentrent sur la conception d'une CDR (Clock and Data Recovery). Nous détaillerons le comparateur de phase qui joue un rôle critique dans un tel système. Cette thèse présente un comparateur de phase ayant comme avantage d'avoir une mode de fenêtrage et une fréquence de fonctionnement réduite. La topologie spéciale utilisée pour la CDR est décrite, et la théorie relative aux oscillateurs verrouillés en injection est expliquée. L'essentiel du travail de recherche s'est concentrée sur la conception et le layout d'une restitution d'horloge dans le domaine millimétrique, à 80 Gbps. Pour cela plusieurs prototypes ont été réalisés en technologie BiCMOS 130 nm de STMicrolectronics.The increasing bandwidth demand for telecommunication leads to an important rise of serial link operating frequencies. This demand is also present in embedded systems with the growth of devices and peripherals performances. To ensure the data stream is well recovered, a clock and data recovery (CDR) circuit is placed before any logical blocks on the receiver side. The research activities presented in this thesis are related to the design of such a CDR. The phase detector plays a critical role in the CDR circuit and is specially studied. This thesis presents a phase comparator that provides an enhancement by introducing a windowed mode and reducing its operating frequency. The used CDR has a special topology, which is described, and the injection locked oscillator theory is explained. Most of the research of this study has focused on the design and layout of a 80 Gbps CDR. Several prototypes are realized in 130 nm SiGe process from STMicroelectronics.BORDEAUX1-Bib.electronique (335229901) / SudocSudocFranceF

Event-Driven Simulation Methodology for Analog/Mixed-Signal Systems

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2015. 8. 김재하.Recent system-on-chip's (SoCs) are composed of tightly coupled analog and digital components. The resulting mixed-signal systems call for efficient system-level behavioral simulators for fast and systematic verifications. As the system-level verifications rely heavily on digital verification tools, it is desirable to build the mixed-signal simulator based on a digital simulator. However, the existing solutions in digital simulators suffer from a trade-off between simulation speed and accuracy. This work breaks down the trade-off and realizes a fast and accurate analog/mixed-signal behavior simulation in a digital simulator SystemVerilog. The main difference of the proposed methodology from existing ones is its way of representing continuous-time signals. Specifically, a clock signal expresses accurate timing information by carrying an additional real-value time offset, and an analog signal represents its continuous-time waveform in a functional form by employing a set of coefficients. With these signal representations, the proposed method accurately simulates mixed-signal behaviors independently of a simulator's time-step and achieves a purely event-driven simulation without involving any numerical iteration. The speed and accuracy of the proposed methodology are examined for various types of analog/mixed-signal systems. First, timing-sensitive circuits (a phase-locked loops and a clock and data recovery loop) and linear analog circuits (a channel and linear equalizers) are simulated in a high-speed I/O interface example. Second, a switched-linear-behavior simulation is demonstrated through switching power supplies, such as a boost converter and a switched-capacitor converter. Additionally, the proposed method is applied to weakly nonlinear behaviors modeled with a Volterra series for an RF power amplifier and a high-speed I/O linear equalizer. Furthermore, the nonlinear behavior simulation is extended to three different types of injection-locked oscillators exhibiting time-varying nonlinear behaviors. The experimental results show that the proposed simulation methodology achieved tens to hundreds of speed-ups while maintaining the same accuracy as commercial analog simulators.ABSTRACT I CONTENTS III LIST OF FIGURES V LIST OF TABLES XII CHAPTER 1 INTRODUCTION 1 1.1 BACKGROUND 1 1.2 MAIN CONTRIBUTION 6 1.3 THESIS ORGANIZATION 8 CHAPTER 2 EVENT-DRIVEN SIMULATION OF ANALOG/MIXED-SIGNAL BEHAVIORS 9 2.1 PROPOSED CLOCK AND ANALOG SIGNAL REPRESENTATIONS 10 2.2 SIGNAL TYPE DEFINITIONS IN SYSTEMVERILOG 14 2.3 EVENT-DRIVEN SIMULATION METHODOLOGY 16 CHAPTER 3 HIGH-SPEED I/O INTERFACE SIMULATION 21 3.1 CHARGE-PUMP PHASE-LOCKED LOOP 23 3.2 BANGBANG CLOCK AND DATA RECOVERY 37 3.3 CHANNEL AND EQUALIZERS 45 3.4 HIGH-SPEED I/O SYSTEM SIMULATION 52 CHAPTER 4 SWITCHING POWER SUPPLY SIMULATION 55 4.1 BOOST CONVERTER 57 4.2 TIME-INTERLEAVED SWITCHED-CAPACITOR CONVERTER 66 CHAPTER 5 VOLTERRA SERIES MODEL SIMULATION 72 5.1 VOLTERRA SERIES MODEL 74 5.2 CLASS-A POWER AMPLIFIER 79 5.3 CONTINUOUS-TIME EQUALIZER 84 CHAPTER 6 INJECTION-LOCKED OSCILLATOR SIMULATION 89 6.1 PPV-BASED ILO MODEL 91 6.2 LC OSCILLATOR 99 6.3 RING OSCILLATOR 104 6.4 BURST-MODE CLOCK AND DATA RECOVERY 109 CONCLUSION 116 BIBLIOGRAPHY 118 초 록 126Docto

Layout-accurate Ultra-fast System-level Design Exploration Through Verilog-ams

This research addresses problems in designing analog and mixed-signal (AMS) systems by bridging the gap between system-level and circuit-level simulation by making simulations fast like system-level and accurate like circuit-level. The tools proposed include metamodel integrated Verilog-AMS based design exploration flows. The research involves design centering, metamodel generation flows for creating efficient behavioral models, and Verilog-AMS integration techniques for model realization. The core of the proposed solution is transistor-level and layout-level metamodeling and their incorporation in Verilog-AMS. Metamodeling is used to construct efficient and layout-accurate surrogate models for AMS system building blocks. Verilog-AMS, an AMS hardware description language, is employed to build surrogate model implementations that can be simulated with industrial standard simulators. The case-study circuits and systems include an operational amplifier (OP-AMP), a voltage-controlled oscillator (VCO), a charge-pump phase-locked loop (PLL), and a continuous-time delta-sigma modulator (DSM). The minimum and maximum error rates of the proposed OP-AMP model are 0.11 % and 2.86 %, respectively. The error rates for the PLL lock time and power estimation are 0.7 % and 3.0 %, respectively. The OP-AMP optimization using the proposed approach is ~17000× faster than the transistor-level model based approach. The optimization achieves a ~4× power reduction for the OP-AMP design. The PLL parasitic-aware optimization achieves a 10× speedup and a 147 µW power reduction. Thus the experimental results validate the effectiveness of the proposed solution

Source-synchronous I/O Links using Adaptive Interface Training for High Bandwidth Applications

Mobility is the key to the global business which requires people to be always connected to a central server. With the exponential increase in smart phones, tablets, laptops, mobile traffic will soon reach in the range of Exabytes per month by 2018. Applications like video streaming, on-demand-video, online gaming, social media applications will further increase the traffic load. Future application scenarios, such as Smart Cities, Industry 4.0, Machine-to-Machine (M2M) communications bring the concepts of Internet of Things (IoT) which requires high-speed low power communication infrastructures. Scientific applications, such as space exploration, oil exploration also require computing speed in the range of Exaflops/s by 2018 which means TB/s bandwidth at each memory node. To achieve such bandwidth, Input/Output (I/O) link speed between two devices needs to be increased to GB/s. The data at high speed between devices can be transferred serially using complex Clock-Data-Recovery (CDR) I/O links or parallely using simple source-synchronous I/O links. Even though CDR is more efficient than the source-synchronous method for single I/O link, but to achieve TB/s bandwidth from a single device, additional I/O links will be required and the source-synchronous method will be more advantageous in terms of area and power requirements as additional I/O links do not require extra hardware resources. At high speed, there are several non-idealities (Supply noise, crosstalk, Inter- Symbol-Interference (ISI), etc.) which create unwanted skew problem among parallel source-synchronous I/O links. To solve these problems, adaptive trainings are used in time domain to synchronize parallel source-synchronous I/O links irrespective of these non-idealities. In this thesis, two novel adaptive training architectures for source-synchronous I/O links are discussed which require significantly less silicon area and power in comparison to state-of-the-art architectures. First novel adaptive architecture is based on the unit delay concept to synchronize two parallel clocks by adjusting the phase of one clock in only one direction. Second novel adaptive architecture concept consists of Phase Interpolator (PI)-based Phase Locked Loop (PLL) which can adjust the phase in both direction and achieve faster synchronization at the expense of added complexity. With an increase in parallel I/O links, clock skew which is generated by the improper clock tree, also affects the timing margin. Incorrect duty cycle further reduces the timing margin mainly in Double Data Rate (DDR) systems which are generally used to increase the bandwidth of a high-speed communication system. To solve clock skew and duty cycle problems, a novel clock tree buffering algorithm and a novel duty cycle corrector are described which further reduce the power consumption of a source-synchronous system

Phase Noise in CMOS Phase-Locked Loop Circuits

Phase-locked loops (PLLs) have been widely used in mixed-signal integrated circuits. With the continuously increasing demand of market for high speed, low noise devices, PLLs are playing a more important role in communications. In this dissertation, phase noise and jitter performances are investigated in different types of PLL designs. Hot carrier and negative bias temperature instability effects are analyzed from simulations and experiments. Phase noise of a CMOS phase-locked loop as a frequency synthesizer circuit is modeled from the superposition of noises from its building blocks: voltage-controlled oscillator, frequency divider, phase-frequency detector, loop filter and auxiliary input reference clock. A linear time invariant model with additive noise sources in frequency domain is presented to analyze the phase noise. The modeled phase noise results are compared with the corresponding experimentally measured results on phase-locked loop chips fabricated in 0.5 m n-well CMOS process. With the scaling of CMOS technology and the increase of electrical field, MOS transistors have become very sensitive to hot carrier effect (HCE) and negative bias temperature instability (NBTI). These two reliability issues pose challenges to designers for designing of chips in deep submicron CMOS technologies. A new strategy of switchable CMOS phase-locked loop frequency synthesizer is proposed to increase its tuning range. The switchable PLL which integrates two phase-locked loops with different tuning frequencies are designed and fabricated in 0.5 µm CMOS process to analyze the effects under HCE and NBTI. A 3V 1.2 GHz programmable phase-locked loop frequency synthesizer is designed in 0.5 μm CMOS technology. The frequency synthesizer is implemented using LC voltage-controlled oscillator (VCO) and a low power dual-modulus prescaler. The LC VCO working range is from 900MHz to 1.4GHz. Current mode logic (CML) is used in designing high speed D flip-flop in the dual-modulus prescaler circuits for low power consumption. The power consumption of the PLL chip is under 30mW. Fully differential LC VCO is used to provide high oscillation frequency. A new design of LC VCO using carbon nanotube (CNT) wire inductor has been proposed. The PLL design using CNT-LC VCO shows significant improvement in phase noise due to high-Q LC circuit

Investigation of high bandwith biodevices for transcutaneous wireless telemetry

PhD ThesisBIODEVICE implants for telemetry are increasingly applied today in various areas applications. There are many examples such as; telemedicine, biotelemetry, health care, treatments for chronic diseases, epilepsy and blindness, all of which are using a wireless infrastructure environment. They use microelectronics technology for diagnostics or monitoring signals such as Electroencephalography or Electromyography. Conceptually the biodevices are defined as one of these technologies combined with transcutaneous wireless implant telemetry (TWIT). A wireless inductive coupling link is a common way for transferring the RF power and data, to communicate between a reader and a battery-less implant. Demand for higher data rate for the acquisition data returned from the body is increasing, and requires an efficient modulator to achieve high transfer rate and low power consumption. In such applications, Quadrature Phase Shift Keying (QPSK) modulation has advantages over other schemes, and double the symbol rate with respect to Binary Phase Shift Keying (BPSK) over the same spectrum band. In contrast to analogue modulators for generating QPSK signals, where the circuit complexity and power dissipation are unsuitable for medical purposes, a digital approach has advantages. Eventually a simple design can be achieved by mixing the hardware and software to minimize size and power consumption for implantable telemetry applications. This work proposes a new approach to digital modulator techniques, applied to transcutaneous implantable telemetry applications; inherently increasing the data rate and simplifying the hardware design. A novel design for a QPSK VHDL modulator to convey a high data rate is demonstrated. Essentially, CPLD/FPGA technology is used to generate hardware from VHDL code, and implement the device which performs the modulation. This improves the data transmission rate between the reader and biodevice. This type of modulator provides digital synthesis and the flexibility to reconfigure and upgrade with the two most often languages used being VHDL and Verilog (IEEE Standard) being used as hardware structure description languages. The second objective of this thesis is to improve the wireless coupling power (WCP). An efficient power amplifier was developed and a new algorithm developed for auto-power control design at the reader unit, which monitors the implant device and keeps the device working within the safety regulation power limits (SAR). The proposed system design has also been modeled and simulated with MATLAB/Simulink to validate the modulator and examine the performance of the proposed modulator in relation to its specifications.Higher Education Ministry in Liby

Modellierung der Zuverlässigkeit bei Entwurf und Verifikation von Mixed-Signal-Schaltungen

Die zunehmende Verbreitung von Elektronik im Alltag und die weitere Verringerung der Strukturgrößen stellen neue Anforderungen an die Zuverlässigkeit und Verfügbarkeit integrierter Schaltungen. Die Arbeit zeigt ein systematisches Vorgehen zur Modellierung des funktionalen Schaltungsverhaltens und ergänzt es um neue Verfahren zur Berücksichtigung zuverlässigkeitsrelevanter Schaltungseigenschaften. Etablierte Verfahren aus der Mechanik zur Behandlung der Zuverlässigkeit werden auf die Degradationseffekte integrierter Halbleiterbauelemente angewandt. Entsprechende Lebensdauermodelle zu relevanten Degradationsmechanismen sind dargestellt. Ausgehend davon werden allgemeine Maße zur Zuverlässigkeitsbewertung von Bauelementen unter Anwendungsbedingungen abgeleitet. Die Diskussion von Methoden zur Analyse der Zuverlässigkeit ganzer Schaltungen im Entwurf rundet die Darstellung ab. Die entwickelten Verfahren dienen der Unterstützung eines schnellen und fehlerfreien Entwurfs sicherer und zuverlässiger Schaltungen. Die Optimierung einer Schaltung hinsichtlich ihres Alterungsverhaltens verdeutlicht diesen Nutzen.The widespread use of electronics in everyday life and its ongoing miniaturization poses new demands in terms of reliability and dependability of integrated circuits. Modeling as a means to support circuit and system design has been used for many years, mainly to represent the functional behavior. This thesis aims at the following objectives: • For known modeling techniques regarding the functional behavior a systematic methodology is developed and structured in an integrated modelling flow. • The developed methodology is extended by modeling non-functional characteristics particularly with regard to reliability. In this work reliability modeling covers primarily degradation effects that occur during normal operation and affect the electrical behavior of integrated devices. As an important precondition for the developed methods to consider electrical degradation, linear damage accumulation is assumed. That is, the sequence in time of the applied stress is not important, the damage accumulates linearly over time. As a result a systematic process to model the functional behavior of analog and mixed signal circuits is presented. It is amended by new methods to include reliability relevant characteristics of the circuit. Established methods from mechanical engineering to describe and analyze reliability are adopted and applied to the degradation effects of integrated semiconductor devices. Respective lifetime models for relevant degradation effects are presented. Starting from a generic model structure general measures are derived to assess reliability of devices exposed to application conditions. In addition methods to analyze reliability of large circuits in the design process are discussed. The developed methods support a fast and correct design of safe and reliable circuits. As an example the optimization of a circuit with respect to its degradation behavior is demonstrated.Die zunehmende Verbreitung von Elektronik im Alltag und die weitere Verringerung der Strukturgrößen stellt neue Anforderungen an die Zuverlässigkeit und Verfügbarkeit integrierter Schaltungen. Modellierung zur Unterstützung des Schaltkreis- und Systementwurfs wird seit langer Zeit eingesetzt, bisher hauptsächlich zur Nachbildung des funktionalen Verhaltens einer Schaltung. Die vorliegende Arbeit verfolgt zwei Ziele: • Zu bekannten Modellierungsverfahren für das funktionale Verhalten wird eine Systematik entwickelt und in einen durchgängigen Modellierungsablauf abgebildet. • Die Methodik wird um die Modellierung nichtfunktionaler Eigenschaften erweitert, insbesondere werden Verfahren zur Berücksichtigung der Zuverlässigkeit entwickelt. Für die Zuverlässigkeitsmodellierung werden in erster Linie Degradationseffekte betrachtet, die während des bestimmungsgemäßen Betriebs entstehen und sich auf das elektrische Verhalten integrierter Bauelemente auswirken. Als eine wesentliche Voraussetzung für die entwickelten Verfahren zur Berücksichtigung der elektrischen Degradation wird lineare Schadensakkumulation angenommen. Dies bedeutet, dass die zeitliche Abfolge des anliegenden Stresses keine Rolle spielt, sondern sich die entstehende Schädigung linear akkumuliert. Das Ergebnis der Arbeit ist eine systematische Vorgehensweise zur Modellierung des funktionalen Verhaltens von analogen und Mixed-Signal-Schaltungen. Diese wird ergänzt um neue Verfahren zur Berücksichtigung zuverlässigkeitsrelevanter Eigenschaften der Schaltung. Analogien zur Mechanik erlauben es, in diesem Bereich etablierte Vorgehensweisen zur Beschreibung und Analyse der Zuverlässigkeit zu übernehmen und auf die Degradationseffekte integrierter Halbleiterbauelemente anzuwenden. Entsprechende Lebensdauermodelle zu relevanten Degradationsmechanismen sind dargestellt. Ausgehend von der generellen Struktur solcher Modelle werden allgemeine Maße zur Zuverlässigkeitsbewertung von Bauelementen unter Anwendungsbedingungen abgeleitet. Die Diskussion von Methoden zur Analyse der Zuverlässigkeit ganzer Schaltungen im Entwurf rundet die Darstellung ab. Die entwickelten Verfahren dienen der Unterstützung eines schnellen und fehlerfreien Entwurfs sicherer und zuverlässiger Schaltungen. Anhand der Optimierung einer Schaltung auf der Grundlage ihres Alterungsverhaltens wird dieser Nutzen verdeutlicht