차세대 자동차용 카메라 데이터 통신을 위한 비대칭 동시 양방향 송수신기의 설계

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022.2. 정덕균.본 학위 논문에서는 차세대 자동차용 카메라 링크를 위해 높은 속도의 4레벨 펄스 진폭 변조 신호와 낮은 속도의 2레벨 펄스 진폭 변조 신호를 통신하는 비대칭 동시 양방향 송수신기의 설계 기술에 대해 제안하고 검증되었다. 첫번째 프로토타입 설계에서는, 10B6Q 직류 밸런스 코드를 탑재한 4레벨 펄스 진폭 변조 송신기와 고정된 데이터와 참조 레벨을 가지는 4레벨 펄스 진폭 변조 적응형 수신기에 대한 내용이 기술되었다. 4레벨 펄스 진폭 변조 송신기에서는 교류 연결 링크 시스템에 대응하기 위한 면적 및 전력 효율성이 좋은 10B6Q 코드가 제안되었다. 이 코드는 직류 밸런스를 맞추고 연속적으로 같은 심볼을 가지는 길이를 6개로 제한 시킨다. 비록 여기서는 입력 데이터 길이 10비트를 사용하였지만, 제안된 기술은 카메라의 다양한 데이터 타입에 대응할 수 있도록 입력 데이터 길이에 대한 확장성을 가진다. 반면, 4레벨 펄스 진폭 변조 적응형 수신기에서는, 샘플러의 옵셋을 최적으로 제거하여 더 낮은 비트에러율을 얻기 위해서, 기존의 데이터 및 참조 레벨을 조절하는 대신, 이 레벨들은 고정시키고 가변 게인 증폭기를 적응형으로 조절하도록 하였다. 상기 10B6Q 코드 및 고정 데이터 및 참조레벨 기술을 가진 프로토타입 칩들은 40 나노미터 상호보완형 메탈 산화 반도체 공정으로 제작되었고 칩 온 보드 형태로 평가되었다. 10B6Q 코드는 합성 게이트 숫자는 645개와 함께 단 0.0009 mm2 의 면적 만을 차지한다. 또한, 667 MHz 동작 주파수에서 단 0.23 mW 의 전력을 소모한다. 10B6Q 코드를 탑재한 송신기에서 8-Gb/s 4레벨 펄스 진폭 변조 신호를 고정 데이터 및 참조 레벨을 가지는 적응형 수신기로 12-m 케이블 (22-dB 채널 로스) 을 통해서 보낸 결과 최소 비트 에러율 108 을 달성하였고, 비트 에러율 105 에서는 아이 마진이 0.15 UI x 50 mV 보다 크게 측정되었다. 송수신기를 합친 전력 소모는 65.2 mW (PLL 제외) 이고, 성과의 대표수치는 0.37 pJ/b/dB 를 보여주었다. 첫번째 프로토타입 설계을 포함하여 개선된 두번째 프로토타입 설계에서는, 12-Gb/s 4레벨 펄스 진폭 변조 정방향 채널 신호와 125-Mb/s 2레벨 펄스 진폭 변조 역방향 채널 신호를 탑재한 비대칭 동시 양방향 송수신기에 대해 기술되고 검증되었다. 제안된 넓은 선형 범위를 가지는 하이브리드는 gmC 저대역 통과 필터와 에코 제거기와 함께 아웃바운드 신호를 24 dB 이상 효율적으로 감소시켰다. 또한, 넓은 선형 범위를 가지는 하이브리드와 함께 게인 감소기를 형성하게 되는 선형 범위 증폭기를 통해 4레벨 펄스 진폭 변조 신호의 선형성과 진폭의 트레이드 오프 관계를 깨는 것이 가능하였다. 동시 양방향 송수신기 칩은 40 나노미터 상호보완형 메탈 산화 반도체 공정으로 제작되었다. 상기 설계 기술들을 이용하여, 4레벨 펄스 진폭 변조 및 2레벨 펄스 진폭 변조 송수신기 모두 5m 채널 (채널 로스 15.9 dB) 에서 1E-12 보다 낮은 비트 에러율을 달성하였고, 총 78.4 mW 의 전력 소모를 기록하였다. 종합적인 송수신기는 성과 대표지표로 0.41 pJ/b/dB 와 함께 동시 양방향 통신 아래에서 4레벨 펄스 진폭 변조 신호 및 2레벨 펄스 진폭 변조 신호 각각에서 아이 마진 0.15 UI 와 0.57 UI 를 달성하였다. 이 수치는 성과 대표지표 0.5 이하를 가지는 기존 동시 양방향 송수신기와의 비교에서 최고의 아이 마진을 기록하였다.In this dissertation, design techniques of a highly asymmetric simultaneous bidirectional (SB) transceivers with high-speed PAM-4 and low-speed PAM-2 signals are proposed and demonstrated for the next-generation automotive camera link. In a first prototype design, a PAM-4 transmitter with 10B6Q DC balance code and a PAM-4 adaptive receiver with fixed data and threshold levels (dtLevs) are presented. In PAM-4 transmitter, an area- and power-efficient 10B6Q code for an AC coupled link system that guarantees DC balance and limited run length of six is proposed. Although the input data width of 10 bits is used here, the proposed scheme has an extensibility for the input data width to cover various data types of the camera. On the other hand, in the PAM-4 adaptive receiver, to optimally cancel the sampler offset for a lower BER, instead of adjusting dtLevs, the gain of a programmable gain amplifier is adjusted adaptively under fixed dtLevs. The prototype chips including above proposed 10B6Q code and fixed dtLevs are fabricated in 40-nm CMOS technology and tested in chip-on-board assembly. The 10B6Q code only occupies an active area of 0.0009 mm2 with a synthesized gate count of 645. It also consumes 0.23 mW at the operating clock frequency of 667 MHz. The transmitter with 10B6Q code delivers 8-Gb/s PAM-4 signal to the adaptive receiver using fixed dtLevs through a lossy 12-m cable (22-dB channel loss) with a BER of 1E-8, and the eye margin larger than 0.15 UI x 50 mV is measured for a BER of 1E-5. The proto-type chips consume 65.2 mW (excluding PLL), exhibiting an FoM of 0.37 pJ/b/dB. In a second prototype design advanced from the first prototypes, An asymmetric SB transceivers incorporating a 12-Gb/s PAM-4 forward channel and a 125-Mb/s PAM-2 back channel are presented and demonstrated. The proposed wide linear range (WLR) hybrid combined with a gmC low-pass filter and an echo canceller effectively suppresses the outbound signals by more than 24dB. In addition, linear range enhancer which forms a gain attenuator with WLR hybrid breaks the trade-off between the linearity and the amplitude of the PAM-4 signal. The SB transceiver chips are separately fabricated in 40-nm CMOS technology. Using above design techniques, both PAM-4 and PAM-2 SB transceivers achieve BER less than 1E-12 over a 5-m channel (15.9 dB channel loss), consuming 78.4 mW. The overall transceivers achieve an FoM of 0.41 pJ/b/dB and eye margin (at BER of 1E-12) of 0.15 UI and 0.57 UI for the forward PAM-4 and back PAM-2 signals, respectively, under SB communication. This is the best eye margin compared to the prior art SB transceivers with an FoM less than 0.5.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 DISSERTATION ORGANIZATION 4 CHAPTER 2 BACKGROUND ON AUTOMOTIVE CAMERA LINK 6 2.1 OVERVIEW 6 2.2 SYSTEM REQUIREMENTS 10 2.2.1 CHANNEL 10 2.2.2 POWER OVER DIFFERENTIAL LINE (PODL) 12 2.2.3 AC COUPLING AND DC BALANCE CODE 15 2.2.4 SIMULTANEOUS BIDIRECTIONAL COMMUNICATION 18 2.2.4.1 HYBRID 18 2.2.4.2 ECHO CANCELLER 20 2.2.5 ADAPTIVE RECEIVE EQUALIZATION 22 CHAPTER 3 AREA AND POWER EFFICIENT 10B6Q ENCODER FOR DC BALANCE 25 3.1 INTRODUCTION 25 3.2 PRIOR WORKS 28 3.3 PROPOSED AREA- AND POWER-EFFICIENT 10B6Q PAM-4 CODER 30 3.4 DESIGN OF THE 10B6Q CODE 33 3.4.1 PAM-4 DC BALANCE 35 3.4.2 PAM-4 TRANSITION DENSITY 35 3.4.3 10B6Q DECODER 37 3.5 IMPLEMENTATION AND MEASUREMENT RESULTS 40 CHAPTER 4 PAM-4 TRANSMITTER AND ADAPTIVE RECEIVER WITH FIXED DATA AND THRESHOLD LEVELS 45 4.1 INTRODUCTION 45 4.2 PRIOR WORKS 47 4.3 ARCHITECTURE AND IMPLEMENTATION 49 4.2.1 PAM-4 TRANSMITTER 49 4.2.2 PAM-4 ADAPTIVE RECEIVER 52 4.3 MEASUREMENT RESULTS 62 CHAPTER 5 ASYMMETRIC SIMULTANEOUS BIDIRECTIONAL TRANSCEIVERS USING WIDE LINEAR RANGE HYBRID 68 5.1 INTRODUCTION 68 5.2 PRIOR WORKS 70 5.3 WIDE LINEAR RANGE (WLR) HYBRID 75 5.3 IMPLEMENTATION 78 5.3.1 SERIALIZER (SER) DESIGN 78 5.3.2 DESERIALIZER (DES) DESIGN 79 5.4 HALF CIRCUIT ANALYSIS OF WLR HYBRID AND LRE 82 5.5 MEASUREMENT RESULTS 88 CHAPTER 6 CONCLUSION 97 BIBLIOGRAPHY 99 초 록 106박

오프셋 제거기의 적응 제어 등화기와 보우-레이트 위상 검출기를 활용한 수신기 설계

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2021.8. 염제완.In this thesis, designs of high-speed, low-power wireline receivers (RX) are explained. To be specific, the circuit techniques of DC offset cancellation, merged-summer DFE, stochastic Baud-rate CDR, and the phase detector (PD) for multi-level signal are proposed. At first, an RX with adaptive offset cancellation (AOC) and merged summer decision-feedback equalizer (DFE) is proposed. The proposed AOC engine removes the random DC offset of the data path by examining the random data stream's sampled data and edge outputs. In addition, the proposed RX incorporates a shared-summer DFE in a half-rate structure to reduce power dissipation and hardware complexity of the adaptive equalizer. A prototype chip fabricated in 40 nm CMOS technology occupies an active area of 0.083 mm2. Thanks to the AOC engine, the proposed RX achieves the BER of less than 10-12 in a wide range of data rates: 1.62-10 Gb/s. The proposed RX consumes 18.6 mW at 10 Gb/s over a channel with a 27 dB loss at 5 GHz, exhibiting a figure-of-merit of 0.068 pJ/b/dB. Secondly, a 40 nm CMOS RX with Baud-rate phase-detector (BRPD) is proposed. The RX includes two PDs: the BRPD employing the stochastic technique and the BRPD suitable for multi-level signals. Thanks to the Baud-rate CDR’s advantage, by not using an edge-sampling clock, the proposed CDR can reduce the power consumption by lowering the hardware complexity. Besides, the proposed stochastic phase detector (SPD) tracks an optimal phase-locking point that maximizes the vertical eye opening. Furthermore, despite residual inter-symbol interference, proposed BRPD for multi-level signal secures vertical eye margin, which is especially vulnerable in the multi-level signal. Besides, the proposed BRPD has a unique lock point with an adaptive DFE, unlike conventional Mueller-Muller PD. A prototype chip fabricated in 40 nm CMOS technology occupies an active area of 0.24 mm2. The proposed PAM-4 RX achieves the bit-error-rate less than 10-11 in 48 Gb/s and the power efficiency of 2.42 pJ/b.본 논문은 고속, 저전력으로 동작하는 유선 수신기의 설계에 대해 설명하고 있다. 구체적으로 말하면, 오프셋 상쇄, 병합된 서머를 사용하는 결정 피드백 등화기 기술, 확률적 보우 레이트 클럭과 데이터 복원기, 그리고 다중 레벨 신호에 적합한 위상 검출기를 제안한다. 첫째로, 적응 오프셋 제거 및 병합된 서머를 사용하는 결정 피드백 등화기를 갖춘 수신기를 제안한다. 제안된 적응 오프셋 제거 엔진은 임의의 데이터 스트림의 샘플링 데이터, 에지 출력을 검사하여 데이터 경로 상의 오프셋을 제거한다. 또한 하프 레이트 구조의 병합된 서머를 사용하는 결정 피드백 등화기는 전력의 사용과 하드웨어의 복잡성을 줄인다. 40 nm CMOS 기술로 제작된 프로토타입 칩은 0.083 mm2 의 면적을 가진다. 적응 오프셋 제거기 덕분에 제안된 수신기는 10-12 미만의 BER을 달성한다. 또한 제안된 수신기는 5GHz에서 27 dB의 로스를 갖는 채널에서 10 Gb/s의 속도에서 18.6 mW를 소비하며 0.068 pJ/b/dB의 FoM을 달성하였다. 두번째로, 보우 레이트 위상 검출기가 있는 40 nm CMOS 수신기가 제안되었다. 수신기에는 두개의 보우 레이트 위상 검출기를 포함한다. 하나는 확률론적 기법을 사용하는 보우 레이트 위상 검출기이다. 보우 레이트 클럭 데이터 복원기의 장점 덕분에 에지 샘플링 클럭을 사용하지 않음으로서 파워의 소모와 하드웨어의 복잡성을 줄였다. 또한 확률적 위상 검출기는 수직 아이 오프닝을 최대화하는 최적의 위상 지점을 찾을 수 있었다. 다른 위상 검출기는 다중 레벨 신호에 적합한 방식이다. 심볼 간 간섭이 다중 레벨 신호에 매우 취약한 문제가 있더라도 제안된 다중 레벨 신호용 보우 레이트 위상 검출기는 수직 아이 마진을 확보한다. 게다가 제안된 보우 레이트 위상 검출기는 기존의 뮬러-뮐러 위상 검출기와 달리 적응형 결정 피드백 등화기가 있더라도 유일한 락 지점을 갖는다. 프로토타입 칩은 0.24mm2의 면적을 가진다. 제안된 PAM-4 수신기는 48 Gb/s의 속도에서 10-11 미만의 BER을 가지고, 2.42 pJ/b의 FoM을 가진다.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 5 CHAPTER 2 BACKGROUNDS 6 2.1 BASIC ARCHITECTURE IN SERIAL LINK 6 2.1.1 SERIAL COMMUNICATION 6 2.1.2 CLOCK AND DATA RECOVERY 8 2.1.3 MULTI-LEVEL PULSE-AMPLITUDE MODULATION 10 2.2 EQUALIZER 12 2.2.1 EQUALIZER OVERVIEW 12 2.2.2 DECISION-FEEDBACK EQUALIZER 15 2.2.3 ADAPTIVE EQUALIZER 18 2.3 CLOCK RECOVERY 21 2.3.1 2X OVERSAMPLING PD ALEXANDER PD 22 2.3.2 BAUD-RATE PD MUELLER MULLER PD 25 CHAPTER 3 AN ADAPTIVE OFFSET CANCELLATION SCHEME AND SHARED SUMMER ADAPTIVE DFE 28 3.1 OVERVIEW 28 3.2 AN ADAPTIVE OFFSET CANCELLATION SCHEME AND SHARED-SUMMER ADAPTIVE DFE FOR LOW POWER RECEIVER 31 3.3 SHARED SUMMER DFE 37 3.4 RECEIVER IMPLEMENTATION 42 3.5 MEASUREMENT RESULTS 45 CHAPTER 4 PAM-4 BAUD-RATE DIGITAL CDR 51 4.1 OVERVIEW 51 4.2 OVERALL ARCHITECTURE 53 4.2.1 PROPOSED BAUD-RATE CDR ARCHITECTURE 53 4.2.2 PROPOSED ANALOG FRONT-END STRUCTURE 59 4.3 STOCHASTIC PHASE DETECTION PAM-4 CDR 64 4.3.1 PROPOSED STOCHASTIC PHASE DETECTION 64 4.3.2 COMPARISON OF THE STOCHASTIC PD WITH SS-MMPD 70 4.4 PHASE DETECTION FOR MULTI-LEVEL SIGNALING 73 4.4.1 PROPOSED BAUD-RATE PHASE DETECTOR FOR MULTI-LEVEL SIGNAL 73 4.4.2 DATA LEVEL AND DFE COEFFICIENT ADAPTATION 79 4.4.3 PROPOSED PHASE DETECTOR 84 4.5 MEASUREMENT RESULT 88 4.5.1 MEASUREMENT OF THE PROPOSED STOCHASTIC BAUD-RATE PHASE DETECTION 94 4.5.2 MEASUREMENT OF THE PROPOSED BAUD-RATE PHASE DETECTION FOR MULTI-LEVEL SIGNAL 97 CHAPTER 5 CONCLUSION 103 BIBLIOGRAPHY 105 초 록 109박

The truth about 2-level transition elimination in bang-bang PAM-4 CDRs

Reception of 4-level pulse amplitude modulation (PAM-4) requires a clock and data recovery (CDR) circuit, typically implemented by a PLL-like structure. An essential block in such a CDR is the phase detector which should detect whether the recovered clock leads or lags the incoming data edges. In typical implementations an incoming data edge is detected by sensing whether the incoming waveform crosses a data threshold level. However, there is some ambiguity in detecting the incoming data edge because PAM-4 modulation has 3 thresholds. If the waveform crosses multiple threshold levels, the level crossings will occur at different time instants due to the finite rise/fall time of the incoming waveform. In this work, we first analyze qualitatively and quantitatively CDR systems that use one threshold for phase adjustment. Here, eliminating the 2-level transitions decreases the amount of jitter injected by the phase detector. However, the available transitions for phase adjustment are also reduced, which lowers the CDR's robustness. Secondly, for CDR systems using three thresholds, a combination of two techniques: majority voting and elimination of 2-level transitions is investigated. We prove that in this case, the elimination of 2-level transitions is not needed and even gives a worse performance when implemented

Advanced Signal Processing for Pulse-Amplitude Modulation Optical Transmission Systems

[ES] Los sistemas de transmisión óptica no-coherente se emplean actualmente en las redes ópticas de corto alcance (< 80 km), como son las redes de ámbito metropolitano. La implementación más común en el estado del arte se basa en sistemas que emplean multiplexación por división en longitud de onda (WDM, wavelength division multiplexing) de cuatro longitudes de onda (¿) proporcionando un régimen binario de 100 Gbps (4¿×25 Gbps). En los últimos años, los sistemas de transmisión ópticos no-coherentes están evolucionando desde 100 Gbps a 400 Gbps (4¿×100 Gbps). Dado que este mercado comprende un gran número de sistemas, el coste es un parámetro importante que debe ser lo más bajo posible. El objetivo de esta tesis es investigar distintos aspectos del procesado de señal en general y, específicamente, investigar nuevas técnicas de procesado digital de señal (DSP, digital signal processing) que puedan ser utilizadas en sistemas de transmisión óptica no-coherentes empleando la modulación por amplitud de pulsos (PAM, pulse-amplitude modulation). Para que una técnica DSP sea interesante en el contexto de una red óptica WDM no-coherente, esta debe mitigar de manera efectiva al menos una de las tres limitaciones principales que afectan a estos sistemas: limitaciones de ancho de banda, limitaciones por dispersión cromática (CD), y el ruido. En esta tesis se proponen y examinan una serie de algoritmos cuyo su rendimiento es analizado mediante simulación y experimentalmente en laboratorio: - Feed-forward equalizer (FFE): este es el esquema de ecualización más común que se emplea principalmente en las transmisiones ópticas no-coherentes de alto régimen binario. Puede compensar grandes limitaciones en el ancho de banda. - Estimación de la secuencia de máxima verosimilitud (MLSE): el MLSE es un detector óptimo y, por lo tanto, proporciona las mejores prestaciones en detección cuando se abordan las limitaciones por CD y de ancho de banda. - Conformación geométrica de la constelación: en los esquemas de modulación de intensidad óptica multinivel, la distancia entre los niveles de amplitud puede ajustarse adecuadamente (de manera que no son equidistantes) a fin de aumentar la tolerancia de la señal frente al ruido. - Conformación probabilística: técnica diseñada específicamente para esquemas de modulación multinivel. Esta técnica ajusta la probabilidad de cada nivel de amplitud de modo que se incrementa la tolerancia al ruido óptico. - Señalización de respuesta parcial (PRS, partial signaling response): este es un enfoque basado en DSP donde una interferencia entre símbolos (ISI, inter-symbol interference) controlada es introducida intencionalmente de tal manera que la señal resultante requiere menos ancho de banda. La técnica PRS puede adaptarse para combatir también el efecto de CD. - Pre-énfasis digital (DPE, digital pre-emphasis): esta técnica consiste en aplicar el inverso de la función de transferencia del sistema a la señal en el transmisor, lo que reduce el impacto de las limitaciones de ancho de banda en el receptor. - Modulación con codificación Trellis (TCM, Trellis-coded modulation): esquema de modulación que combina elementos de corrección de errores (FEC, forward error correction) con técnicas de partición en conjuntos y modulación multidimensional para generar una señal más resistente al ruido. - Modulación multidimensional por partición en conjuntos: muy similar a TCM, pero sin ningún elemento FEC. Tiene menos ganancias que TCM en términos de tolerancia al ruido, pero no es tan sensible al ISI. Utilizando estas técnicas, esta tesis demuestra que es posible lograr una transmisión óptica con régimen binario de 100 Gbps/¿ empleando componentes de bajo coste. En esta tesis también demuestra regímenes binarios de más de 200 Gbps, lo que indica que la transmisión óptica no-coherente con modulación PAM puede ser una solución viable y eficiente en coste[CA] Actualment, s'utilitzen sistemes òptics no coherents en xarxes òptiques de curt abast ( < 80 km), com són les xarxes d'àmbit metropolità. La implementació més comuna que podem trobar en l'estat de l'art es correspon amb sistemes emplenant multiplexació per divisió en longitud d'ona (WDM, wavelength division multiplexing) de quatre longituds d'ona (¿) proporcionant un règim binari de 100 Gbps (4¿×25 Gbps). En els últims anys, els sistemes de transmissió òptica no-coherents han evolucionat des de 100 Gbps cap a 400 Gbps (100 Gbps/¿). Atès que el mercat de sistemes de curt abast compren un gran volum de dispositius òptics instal·lats, el cost unitari és molt important i ha de ser el més baix possible. L'objectiu d'aquesta tesi és analitzar aspectes del processament de senyal en general i, específicament, investigar noves tècniques de processament digital de senyal (DSP, digital signal processing) que puguen ser utilitzades en sistemes de transmissió òptica no-coherent que utilitzen la modulació per amplitud d'impulsos (PAM, pulse-amplitude modulation). Per tal que una tècnica DSP es considere interessant per a una xarxa òptica WDM no-coherent, aquesta ha de mitigar efectivament almenys una de les tres principals limitacions que afecten aquests sistemes: limitacions d'ample de banda, limitacions per dispersió cromàtica (CD), i el soroll. En aquesta tesi s'examinen una sèrie d'algoritmes, el seu rendiment s'analitza per simulació i experimentalment en laboratori: - Feed-forward equalizer (FFE): aquest és l'esquema d'equalització més comú i s'utilitza bàsicament en les transmissions òptiques no coherents d'alt règim binari. Pot compensar grans quantitats de limitacions d'ample de banda. - Estimació de la seqüència de probabilitat màxima (MLSE): el MLSE és un detector òptim i, per tant, proporciona el millor rendiment quan es tracta de limitacions d'ample de banda i de CD. - Conformació geomètrica de la constel·lació: en esquemes de modulació òptica d'intensitat multinivell es pot ajustar la distància entre els nivells d'amplitud (de manera que ja no són equidistants) per augmentar la tolerància del senyal al soroll. - Conformació probabilística: una tècnica dissenyada específicament per als esquemes de modulació multinivell; ajusta la probabilitat de cada nivell d'amplitud de manera que augmenta la tolerància al soroll òptic. - Senyalització de resposta parcial (PRS, partial signaling response): és un enfocament basat en DSP on la interferència entre símbols (ISI, inter-symbol interference) controlada s'introdueix intencionalment de manera que el senyal resultant requereix menys ample de banda. La tècnica PRS es pot adaptar per combatre els efectes del CD. - Pre-èmfasi digital (DPE, digital pre-emphasis): aquesta tècnica consisteix a aplicar la inversió de la funció de transferència del sistema a la senyal en el transmissor de manera que es redueix l'impacte de les limitacions d'ample de banda en la senyal en el receptor. - Modulació amb codificació Trellis (TCM, Trellis-coded modulation): esquema de modulació que combina els elements de correcció d'errors avançats (FEC, forward error correction) amb tècniques de partionament de conjunts i modulació multidimensional per generar un senyal més resistent al soroll. - Modulació multidimensional per partició en conjuntes: molt similar a TCM però sense elements FEC. Té guanys menors que TCM en termes de tolerància al soroll, però no és tan sensible a l'ISI. Mitjançant l'ús d'aquestes tècniques, aquesta tesi demostra que és possible aconseguir una transmissió òptica amb un règim binari de 100 Gbps/¿ utilitzant components de baix cost. Esta tesi també demostra règims binaris de més de 200 Gbps, el que indica que la tecnologia no-coherent amb modulació PAM és una solució viable i eficient en cost per a una nova generació de sistemes transceptors òptics WDM funcionant a 800 Gbps (4¿×200 G[EN] Non-coherent optical transmission systems are currently employed in short-reach optical networks (reach shorter than 80 km), like metro networks. The most common implementation in the state-of-the-art is the four wavelength (¿) 100 Gbps (4¿×25 Gbps) wavelength division multiplexing (WDM) transceiver. In recent years non-coherent optical transmissions are evolving from 100 Gbps to 400 Gbps (4¿×100 Gbps). Since in the short-reach market the volume of optical devices being deployed is very large, the cost-per-unit of the devices is very important, and it should be as low as possible. The goal of this thesis is to investigate some general signal processing aspects and, specifically, digital signal processing (DSP) techniques required in non-coherent pulse-amplitude modulation (PAM) optical transmission, and also to investigate novel algorithms which could be applied to this application scenario. In order for a DSP technique to be considered an interesting solution for non-coherent WDM optical networks it has to effectively mitigate at least one of the three main impairments affecting such systems: bandwidth limitations, chromatic dispersion (CD) and noise (in optical or electrical domain). A series of algorithms are proposed and examined in this thesis, and their performance is analyzed by simulation and also experimentally in the laboratory: - Feed-forward equalization (FFE): this is the most common equalizer and it is basically employed in every high-speed non-coherent optical transmission. It can compensate high bandwidth limitations. - Maximum likelihood sequence estimation (MLSE): the MLSE is the optimum detector and thus provides the best performance when it comes to dealing with CD and bandwidth limitations. - Geometrical constellation shaping: in multilevel optical intensity modulation schemes the distance between amplitude levels can be adjusted (such that they are no longer equidistant) in order to increase the signal's tolerance to noise. - Probabilistic shaping: another technique designed specifically for multilevel modulation schemes; it adjusts the probability of each amplitude level such that the tolerance to optical noise is increased. - Partial response signaling (PRS): this is a DSP-based approach where a controlled inter-symbol interference (ISI) is intentionally introduced in such a way that the resulting signal requires less bandwidth. PRS can be customized to also mitigate CD impairment, effectively increasing transmission distances up to three times. - Digital pre-emphasis (DPE): this technique consists in applying the inverse of the transfer function of the system to the signal at the transmitter side which reduces the impact of bandwidth limitations on the signal at the receiver side. - Trellis-coded modulation (TCM): a modulation scheme that combines forward error correction (FEC) elements with set-partitioning techniques and multidimensional modulation to generate a signal that is more resistant to noise. - Multidimensional set-partitioned modulation: very similar with TCM but without any FEC elements. It has lower gains than TCM in terms of noise tolerance but is not so sensitive to ISI. By using the techniques enumerated above, this thesis demonstrates that is possible to achieve 100 Gbps/¿ optical transmission bitrate employing cost-effective components. Even more, bitrates higher than 200 Gbps are also demonstrated, indicating that non-coherent PAM is a viable cost-effective solution for next-generation 800 Gbps (4¿×200 Gbps) WDM transceivers.Prodaniuc, C. (2019). Advanced Signal Processing for Pulse-Amplitude Modulation Optical Transmission Systems [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/117315TESI

An Energy-Efficient Reconfigurable Mobile Memory Interface for Computing Systems

The critical need for higher power efficiency and bandwidth transceiver design has significantly increased as mobile devices, such as smart phones, laptops, tablets, and ultra-portable personal digital assistants continue to be constructed using heterogeneous intellectual properties such as central processing units (CPUs), graphics processing units (GPUs), digital signal processors, dynamic random-access memories (DRAMs), sensors, and graphics/image processing units and to have enhanced graphic computing and video processing capabilities. However, the current mobile interface technologies which support CPU to memory communication (e.g. baseband-only signaling) have critical limitations, particularly super-linear energy consumption, limited bandwidth, and non-reconfigurable data access. As a consequence, there is a critical need to improve both energy efficiency and bandwidth for future mobile devices.;The primary goal of this study is to design an energy-efficient reconfigurable mobile memory interface for mobile computing systems in order to dramatically enhance the circuit and system bandwidth and power efficiency. The proposed energy efficient mobile memory interface which utilizes an advanced base-band (BB) signaling and a RF-band signaling is capable of simultaneous bi-directional communication and reconfigurable data access. It also increases power efficiency and bandwidth between mobile CPUs and memory subsystems on a single-ended shared transmission line. Moreover, due to multiple data communication on a single-ended shared transmission line, the number of transmission lines between mobile CPU and memories is considerably reduced, resulting in significant technological innovations, (e.g. more compact devices and low cost packaging to mobile communication interface) and establishing the principles and feasibility of technologies for future mobile system applications. The operation and performance of the proposed transceiver are analyzed and its circuit implementation is discussed in details. A chip prototype of the transceiver was implemented in a 65nm CMOS process technology. In the measurement, the transceiver exhibits higher aggregate data throughput and better energy efficiency compared to prior works

Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications

As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well

Investigation and analysis of time codes Quarterly report

Optimum time code system analysis including characterization of transmission channels, and signal desig

Deterministic Jitter in Broadband Communication

The past decade has witnessed a drastic change in the design of high-speed serial links. While Silicon fabrication technology has produced smaller, faster transistors, transmission line interconnects between chips and through backplanes have not substantially improved and have a practical bandwidth of around 3GHz. As serial link speeds increase, new techniques must be introduced to overcome the bandwidth limitation and maintain digital signal integrity. This thesis studies timing issues pertaining to bandwidth-limited interconnects. Jitter is defined as the timing uncertainty at a threshold used to detect the digital signal. Reliable digital communication requires minimizing jitter. The analysis and modeling presented here focuses on two types of deterministic jitter. First, dispersion of the digital signal in a bandwidth-limited channel creates data-dependent jitter. Our analysis links data sequences to unique timing deviations through the channel response and is shown for general linear time-invariant systems. A Markov model is constructed to study the impact of jitter on the operation of the serial link and provide insight in circuit performance. Second, an analysis of bounded-uncorrected jitter resulting from crosstalk induced in parallel serial links is presented. Timing equalization is introduced to improve the signal integrity of high-speed links. The analysis of deterministic jitter leads to novel techniques for compensating the timing ambiguity in the received data. Data-dependent jitter equalization is discussed at both the receiver, where it complements the operation of clock and data recovery circuits, and as a phase pre-emphasis technique. Crosstalk-induced, bounded-uncorrected jitter can also be compensated. By detecting electromagnetic modes between neighboring serial links, a transmitter or receiver anticipates the timing deviation that has occurred along the transmission line. Finally, we discuss a new circuit technique for submillimeter integrated circuits. Demands of wireless communication and the high speed of Silicon Germanium transistors provide opportunities for unique radio architectures for submillimeter integrated circuits. Scalable, fully-integrated phased arrays control a radiated beam pattern electronically through tiling multiple chips. Coupled-oscillator arrays are used for the first time to subharmonically injection-lock across a chip or between multiple chips to provide phase coherence across an array.</p