Heterogeneous 2.5D integration on through silicon interposer

© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity

차세대 반도체 배선을 위한 코발트 합금 자가형성 확산방지막 재료 설계 및 전기적 신뢰성에 대한 연구

학위논문(박사) -- 서울대학교대학원 : 공과대학 재료공학부, 2022.2. 주영창.Recently, the resistance-capacitance (RC) delay of the Cu interconnects in metal 1 (M1) level has been increased rapidly due to the reduction of the interconnect linewidth along with the transistor scaling down, and the interconnect reliability becomes a severe issue again. In order to overcome interconnect performance problems and move forward to the next-generation interconnects system, study on low resistivity (ρo) and low electron mean free path (λ) metals was conducted. Generally, metals such as Cobalt (Co), Ruthenium (Ru), and Molybdenum (Mo) are mentioned as candidates for next-generation interconnect materials, and since they have a low ρo × λ value, it is expected that the influence of interface scatterings and surface scattering can be minimized. However, harsh operating environments such as high electric fields, critical Joule heating, and reduction of the pitch size are severely deteriorating the performance of electronic devices as well as device reliability. For example, since time dependent dielectric breakdown (TDDB) problems for next-generation interconnect system have been reported recently, it is necessary to study alternative barrier materials and processes to improve the interconnect reliability. Specifically, extrinsic dielectric breakdown due to penetration of Co metal ions in high electric fields has been reported as a reliability problem to be solved in Co interconnect systems. Therefore, there is a need for new material system design and research on a robust diffusion barrier that prevents metal ions from penetrating into the dielectric, thereby improving the reliability of Co interconnects. Moreover, in order to lower the resistance of the interconnect, it is necessary to develop an ultra-thin barrier. This is because even a barrier with good reliability characteristics will degrade chip performance if it takes up a lot of volume in the interconnect. The recommended thickness for a single diffusion barrier layer is currently reported to be less than 2.5 nm. As a result, it is essential to develop materials that comprehensively consider performance and reliability. In this study, we designed a Co alloy self-forming barrier (SFB) material that can make sure of low resistance and high reliability for Co interconnects, which is attracting attention as a next-generation interconnect system. The self-forming barrier methodology induces diffusion of an alloy dopant at the interface between the metal and the dielectric during the annealing process. And the diffused dopant reacts with the dielectric to form an ultra-thin diffusion barrier. Through this methodology, it is possible to improve reliability by preventing the movement of metal ions. First of all, material design rules were established to screen the appropriate alloy dopants and all CMOS-compatible metals were investigated. Dopant resistivity, intermetallic compound formation, solubility in Co, activity coefficient in Co, and oxidation tendency is considered as the criteria for the dopant to escape from the Co matrix and react at the Co/SiO2 interface. In addition, thermodynamic calculations were performed to predict which phases would be formed after the annealing process. Based on thermodynamic calculations, 5 dopant metals were selected, prioritized for self-forming behavior. And the self-forming material was finally selected through thin film and device analysis. We confirmed that Cr, Zn, and Mn out-diffused to the surface of the thin film structure using X-ray photoelectron spectroscopy (XPS) depth profile and investigated the chemical state of out-diffused dopants through the analysis of a binding energy. Cr shows the most ideal self-forming behavior with the SiO2 dielectric and reacted with oxygen to form a Cr2O3 barrier. In metal-insulator-semiconductor (MIS) structure, out-diffused Cr reacts with SiO2 at the interface and forms a self-formed single layer. It was confirmed that the thickness of the diffusion barrier layer is about 1.2 nm, which is an ultra-thin layer capable of minimizing the total effective resistance. Through voltage-ramping dielectric breakdown (VRDB) tests, Co-Cr alloy showed highest breakdown voltage (VBD) up to 200 % than pure Co. The effect of Cr doping concentration and heat treatment condition applicable to the interconnect process was confirmed. When Cr was doped less than 1 at%, the robust electrical reliability was exhibited. Also, it was found that a Cr2O3 interfacial layer was formed when annealing process was performed at 250 °C or higher for 30 minutes or longer. In other words, Co-Cr alloy is well suited for the interconnect process because current interconnect process temperature is below 400 °C. And when the film thickness was lowered from 150 nm to 20 nm, excellent VBD values were confirmed even at high Cr doping concentration (~7.5 at%). It seems that the amount of Cr present at the Co/SiO2 interface plays a very important role in improving the Cr oxide SFB quality. Physical modeling is necessary to understand the amount of Cr at the interface according to the interconnect volumes and the reliability of the Cr oxide self-forming barrier. TDDB lifetime test also performed and Co-Cr alloy interconnect shows a highly reliable diffusion barrier property of self-formed interfacial layer. The DFT analysis also confirmed that Cr2O3 is a very promising barrier material because it showed a higher energy barrier value than the TiN diffusion barrier currently being studied. A Co-based self-forming barrier was designed through thermodynamic calculations that take performance and reliability into account in interconnect material system. A Co interconnect system with an ultra-thin Cr2O3 diffusion barrier with excellent reliability is proposed. Through this design, it is expected that high-performance interconnects based on robust reliability in the advanced interconnect can be implemented in the near future.최근 반도체 소자 스케일링에 따른 배선 선폭 감소로 M0, M1영역에서의 metal 비저항이 급격히 증가하여 배선에서의 RC delay가 다시 한번 크게 문제가 되고 있다. 이를 해결하기 위해서 차세대 배선 시스템에서는 낮은 비저항과 electron mean free path (EMFP)을 가지는 물질 연구가 진행되었다. 대표적으로 Co, Ru, Mo와 같은 금속들이 차세대 배선 재료 후보로 언급되고 있으며 낮은 ρ0 × λ 값을 갖기 때문에 interface (surface) scattering과 grain boundary scattering 영향을 최소화할 수 있을 것으로 보고 있다. 하지만 가혹한 electrical field와 높은 Joule heating이 발생하는 동작 환경으로 인해 performance뿐만 아니라 소자 신뢰성이 더 열악한 상황에 놓여있다. 예를 들어 차세대 금속에 대한 time dependent dielectric breakdown (TDDB) 신뢰성 문제가 보고되고 있기 때문에 이를 보안할 확산방지막 물질 및 공정연구가 필요하다. 특히 높은 전기장에서 Co ion이 유전체로 침투하여 extrinsic dielectric breakdown 신뢰성 문제가 최근 보고되고 있다. 따라서 금속 이온이 유전체 내부로 침투하는 것을 방지하여, Co 배선의 신뢰성을 향상시킬 수 견고한 확산방지막 개발 및 새로운 배선 시스템 설계가 필요한 시점이다. 또한, 배선 저항을 낮추기 위해서는 매우 얇은 확산방지막 개발이 필요하다. 신뢰성이 좋은 확산방지막이라도 배선에서 많은 영역을 차지할 경우 전체 성능이 저하되기 때문이다. Cu 확산방지막으로 사용되고 있는 TaN 층은 2.5 nm 보다 얇을 경우 신뢰성이 급격히 나빠지므로 2.5 nm보다 얇은 두께의 견고한 확산방지막 개발이 필요하다. 본 연구는 차세대 반도체 배선 물질로 주목받고 있는 Co 금속에 대하여 저저항·고신뢰성을 확보할 수 있는 Co alloy 자가형성 확산방지막 (Co alloy self-forming barrier, SFB) 소재 디자인하였다. 자가형성 확산방지막 방법론은 열처리 과정에서 금속과 유전체 계면에서 도펀트가 확산하게 된다. 그리고 확산되니 도펀트는 얇은 확산방지막을 형성하는 방법론이다. 이 방법론을 통해 금속 이온의 이동을 방지하여 Co 배선 신뢰성을 향상시킬 수 있을 것으로 예상하였다. 우선, Co 합금상에서 적절한 도펀트를 찾기 위해서 CMOS 공정에 적용 가능한 금속들을 선별하였다. 도펀트 저항, 금속간 화합물 형성 여부, Co내 고용도, Co alloy에서의 활성계수, 산화도, Co/SiO2 계면에서의 안정상을 열역학적 계산을 통해서 물질 선정 기준으로 세웠다. 열역학적 계산을 기반으로 9개의 도펀트 금속이 선택되었으며, Co 합금 자가형성 확산방지막 기준에 따라서 우선 순위를 지정하였다. 그리고 최종적으로 박막과 소자 신뢰성 평가를 통해서 가장 적합한 자가형성 확산방지막 물질을 선정하였다. X-ray photoelectron spectroscopy (XPS) 분석을 이용하여 Cr, Zn, Mn이 박막 구조의 표면으로 외부 확산 여부를 확인하고 결합 에너지 분석을 통해 외부로 확산된 도펀트의 화학적 상태를 조사하였다. 분석 결과 Cr, Zn, Mn이 유전체 계면으로 확산되어 산소와 반응하여oxide/silicate 확산 방지막 (e.g. Cr2O3, Zn2SiO4, MnSiO3)을 형성한 것을 확인하였다. 그 중 Cr은 SiO2 유전체와 함께 가장 이상적인 자기 형성 거동을 나타내며 산소와 반응하여 Cr2O3 층을 형성하는 것을 확인하였다. MIS (Metal-Insulator-Semiconductor) 구조에서도 외부로 확산된 Cr은 계면에서 SiO2와 반응하여 Cr2O3 자가형성 확산방지막이 형성되었다. 확산방지층의 두께는 약 1.2nm로 전체 유효저항을 최소화할 수 있는 충분히 얇은 두께를 확보하였다. VRDB (Voltage-Ramping Dielectric Breakdown) 테스트를 통해 Co-Cr 합금은 순수 Co보다 최대 200% 높은 항복 전압 (breakdown voltage)을 보였다. 반도체 배선 공정에 적용할 수 있는 Cr 도핑 농도와 열처리 조건의 영향을 확인하였다. Cr이 1at% 미만으로 도핑되었을 때 우수한 전기적 신뢰성을 나타내었다. 또한, 250℃ 이상에서 30분 이상 열처리를 하였을 때 Cr2O3 계면층이 형성됨을 알 수 있었다. 즉, 현재 배선 공정 온도가 400°C 미만이기 때문에 Co-Cr 합금이 배선 공정에 적용 가능함을 확인하였다. TDDB 수명 테스트도 수행되었으며 Co-Cr 합금 배선은 자체 형성된 계면층의 매우 안정적인 확산 장벽 특성을 보여주었다. DFT 분석은 Cr2O3자가형성 확산방지막이 현재 연구되고 있는 TiN 확산 장벽보다 더 높은 에너지 장벽 값을 보여주기 때문에 매우 유망한 확산방지막임을 보여주었다. 본 연구는 반도채 배선 물질 시스템에서 성능과 신뢰성을 고려한 열역학적 계산을 통해 Co 기반 자가형성 확산방지막을 설계하였다. 실험 결과 신뢰성이 우수하고 아주 얇은 Cr2O3 확산방지막이 있는 Co-Cr 합금이 제안하였다. 물질 설계와 전기적 신뢰성 검증을 Co/Cr2O3/SiO2 물질 시스템을 제안하였고 앞으로의 다가올 차세대 배선에서 구현될 수 있을 것으로 기대된다.Abstract i Table of Contents v List of Tables ix List of Figures xii Chapter 1. Introduction 1 1.1. Scaling down of VLSI systems 1 1.2. Driving force of interconnect system evolution 7 1.3. Driving force of beyond Cu interconnects 11 1.4. Objective of the thesis 18 1.5. Organization of the thesis 21 Chapter 2. Theoretical Background 22 2.1. Evolution of interconnect systems 22 2.1.1. Cu/barrier/low-k interconnect system 22 2.1.2. Process developments for interconnect reliability 27 2.1.3. 3rd generation of interconnect system 31 2.2 Thermodynamic tools for Co self-forming barrier 42 2.2.1 Binary phase diagram 42 2.2.2 Ellingham diagram 42 2.2.3 Activity coefficient 43 2.3. Reliability of Interconnects 45 2.3.1. Current conduction mechanisms in dielectrics 45 2.3.2. Reliability test vehicles 50 2.3.3. Dielectric breakdown assessment 52 2.3.4. Dielectric breakdown mechanisms 55 2.3.5. Reliability test: VRDB and TDDB 56 2.3.6. Lifetime models 57 Chapter 3. Experimental Procedures 60 3.1. Thin film deposition 60 3.1.1. Substrate preparation 60 3.1.2. Oxidation 61 3.1.3. Co alloy deposition using DC magnetron sputtering 61 3.1.4. Annealing process 65 3.2. Thin film characterization 67 3.2.1. Sheet resistance 67 3.2.2. X-ray photoelectron spectroscopy (XPS) 68 3.3. Metal-Insulator-Semiconductor (MIS) device fabrication 70 3.3.1. Patterning using lift-off process 70 3.3.2. TDDB packaging 72 3.4. Reliability analysis 74 3.4.1. Electrical reliability analysis 74 3.4.2. Transmission electron microscopy (TEM) analysis 75 3.5. Computation 76 3.5.1 FactsageTM calculation 76 3.5.2. Density Functional Theory (DFT) calculation 77 Chapter 4. Co Alloy Design for Advanced Interconnects 78 4.1. Material design of Co alloy self-forming barrier 78 4.1.1. Rule of thumb of Co-X alloy 78 4.1.2. Co alloy phase 80 4.1.3. Out-diffusion stage 81 4.1.4. Reaction step with SiO2 dielectric 89 4.1.5. Comparison criteria 94 4.2. Comparison of Co alloy candidates 97 4.2.1. Thin film resistivity evaluation 97 4.2.2. Self-forming behavior using XPS depth profile analysis 102 4.2.3. MIS device reliability test 110 4.3 Summary 115 Chapter 5. Co-Cr Alloy Interconnect with Robust Self-Forming Barrier 117 5.1. Compatibility of Co-Cr alloy SFB process 117 5.1.1. Effect of Cr doping concentration 117 5.1.2. Annealing process condition optimization 119 5.2. Reliability of Co-Cr interconnects 122 5.2.1. VRDB quality test with Co-Cr alloys 122 5.2.2. Lifetime evaluation using TDDB method 141 5.2.3. Barrier mechanism using DFT 142 5.3. Summary 145 Chapter 6. Conclusion 148 6.1. Summary of results 148 6.2. Research perspectives 150 References 151 Abstract (In Korean) 166 Curriculum Vitae 169박

Limitations and opportunities for wire length prediction in gigascale integration

Wires have become a major source of bottleneck in current VLSI designs, and wire length prediction is therefore essential to overcome these bottlenecks. Wire length prediction is broadly classified into two types: macroscopic prediction, which is the prediction of wire length distribution, and microscopic prediction, which is the prediction of individual wire lengths. The objective of this thesis is to develop a clear understanding of limitations to both macroscopic and microscopic a priori, post-placement, pre-routing wire length predictions, and thereby develop better wire length prediction models. Investigations carried out to understand the limitations to macroscopic prediction reveal that, in a given design (i) the variability of the wire length distribution increases with length and (ii) the use of Rent s rule with a constant Rent s exponent p, to calculate the terminal count of a given block size, limits the accuracy of the results from a macroscopic model. Therefore, a new model for the parameter p is developed to more accurately reflect the terminal count of a given block size in placement, and using this, a new more accurate macroscopic model is developed. In addition, a model to predict the variability is also incorporated into the macroscopic model. Studies to understand limitations to microscopic prediction reveal that (i) only a fraction of the wires in a given design are predictable, and these are mostly from shorter nets with smaller degrees and (ii) the current microscopic prediction models are built based on the assumption that a single metric could be used to accurately predict the individual length of all the wires in a design. In this thesis, an alternative microscopic model is developed for the predicting the shorter wires based on a hypothesis that there are multiple metrics that influence the length of the wires. Three different metrics are developed and fitted into a heuristic classification tree framework to provide a unified and more accurate microscopic model.Ph.D.Committee Chair: Dr. Jeff Davis; Committee Member: Dr. James D. Meindl; Committee Member: Dr. Paul Kohl; Committee Member: Dr. Scott Wills; Committee Member: Dr. Sung Kyu Li

Analysis, synthesis, and fabrication of VLSI Si detector arrays for optoelectronic interconnections

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (p. 141-145).by Edward Joseph Ouellette, III.M.S

Automatic synthesis of analog layout : a survey

A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon

Analog layout design automation: ILP-based analog routers

The shrinking design window and high parasitic sensitivity in the advanced technology have imposed special challenges on the analog and radio frequency (RF) integrated circuit design. In this thesis, we propose a new methodology to address such a deficiency based on integer linear programming (ILP) but without compromising the capability of handling any special constraints for the analog routing problems. Distinct from the conventional methods, our algorithm utilizes adaptive resolutions for various routing regions. For a more congested region, a routing grid with higher resolution is employed, whereas a lower-resolution grid is adopted to a less crowded routing region. Moreover, we strengthen its speciality in handling interconnect width control so as to route the electrical nets based on analog constraints while considering proper interconnect width to address the acute interconnect parasitics, mismatch minimization, and electromigration effects simultaneously. In addition, to tackle the performance degradation due to layout dependent effects (LDEs) and take advantage of optical proximity correction (OPC) for resolution enhancement of subwavelength lithography, in this thesis we have also proposed an innovative LDE-aware analog layout migration scheme, which is equipped with our special routing methodology. The LDE constraints are first identified with aid of a special sensitivity analysis and then satisfied during the layout migration process. Afterwards the electrical nets are routed by an extended OPC-inclusive ILP-based analog router to improve the final layout image fidelity while the routability and analog constraints are respected in the meantime. The experimental results demonstrate the effectiveness and efficiency of our proposed methods in terms of both circuit performance and image quality compared to the previous works

Interconnects for future technology generations - conventional CMOS with copper/low-k and beyond

The limitations of the conventional Cu/low-k interconnect technology for use in future ultra-scaled integrated circuits down to 7 nm in the year 2020 are investigated from the power/performance point of view. Compact models are used to demonstrate the impacts of various interconnect process parameters, for instance, the interconnect barrier/liner bilayer thickness and aspect ratio, on the design and optimization of a multilevel interconnect network. A framework to perform a sensitivity analysis for the circuit behavior to interconnect process parameters is created for future FinFET CMOS technology nodes. Multiple predictive cell libraries down to the 7‒nm technology node are constructed to enable early investigation of the electronic chip performance using commercial electronic design automation (EDA) tools with real chip information. Findings indicated new opportunities that arise for emerging novel interconnect technologies from the materials and process perspectives. These opportunities are evaluated based on potential benefits that are quantified with rigorous circuit-level simulations and requirements for key parameters are underlined. The impacts of various emerging interconnect technologies on the performances of emerging devices are analyzed to quantify the realistic circuit- and system-level benefits that these new switches can offer.Ph.D

Materials for high-density electronic packaging and interconnection

Electronic packaging and interconnections are the elements that today limit the ultimate performance of advanced electronic systems. Materials in use today and those becoming available are critically examined to ascertain what actions are needed for U.S. industry to compete favorably in the world market for advanced electronics. Materials and processes are discussed in terms of the final properties achievable and systems design compatibility. Weak points in the domestic industrial capability, including technical, industrial philosophy, and political, are identified. Recommendations are presented for actions that could help U.S. industry regain its former leadership position in advanced semiconductor systems production