Reliability analysis of planar and symmetrical & asymmetrical trench discrete SiC Power MOSFETs

Silicon Carbide MOSFETs are shown in research to outperform Silicon counterparts on many performance metrics, including switching rates and power losses. To further improve their performance, trench and double-trench structures have recently been developed. To replace conventional planar SiC MOSFETs, besides the performance parameters which are mostly stated in datasheets, reliability studies under stress are also needed. This thesis presents a comprehensive comparison between 3rd generation trench SiC power MOSFETs, namely symmetrical double-trench and asymmetrical trench with planar SiC power MOSFETs on four aspects of: switching slew rates (dI/dt & dV/dt), crosstalk characteristics, bias temperature instability and power cycling stability.First, the dynamic performance in both 1st quadrant and 3rd quadrant has been eval- uated on the differences in stress by dI/dt & dV/dt and resultant losses. This is key in understanding many other reliability criterions, i.e. severity of crosstalk induced switchings. In the 1st quadrant, the source current and drain-source voltage switching rates at both turn-ON and turn-OFF are measured under a range of test conditions. Both the symmetrical and asymmetrical trench MOSFETs have up to 2 times faster voltage and current slew rates compared with the planar one. They also indicate only slight changes in switching rate with junction temperature. In the 3rd quadrant, the reverse recovery peak current and total reverse recovery charge are measured with respect to junction temper- ature and load current level. Both the symmetrical and asymmetrical trench MOSFETs have less than half of the reverse recovery charge of that of the planar SiC MOSFET.In the evaluation of crosstalk characteristics, peak shoot-through current and induced gate voltage at crosstalk are measured with respect to junction temperature and external gate resistance. With particularly large external gate resistances connected to intentionally induce parasitic turn-ON, the symmetrical double-trench MOSFET is shown to be more prone to crosstalk with 23 A peak shoot-through current measured while it is only 10 A for asymmetrical trench and 4 A for planar MOSFET under similar test conditions. As the temperature increase, the peak shoot-through current drops for the symmetrical double-trench, while constant for the asymmetrical trench and rising for the planar device.Threshold voltage drift is also measured to reflect the degradation happened with bias temperature instability at various junction temperatures, stressing voltages and time periods. Under low-magnitude gate stress (within the range of datasheets) in both positive and negative bias cases, there is more threshold drift observed on the two trench MOSFETs at all junction temperatures than the planar MOSFET. When the stress magnitude is raised, there is less threshold drift observed on the two trench MOSFETs.To evaluate the ruggedness in continuous switchings, the devices are placed under repetitive turn-ON events. The thermal performance under such operation are compared. The asymmetrical trench MOSFET experiences the highest case temperature rise while the least is observed for the planar MOSFET. With an external heatsink equipped to achieve more efficient cooling, the repetitive turn-ON test transforms into the conventional power cycling. In this condition, both the symmetrical and asymmetrical trench MOSFETs fail earlier than the degraded (but not failed) planar MOSFET

SiC power MOSFETs performance, robustness and technology maturity

Relatively recently, SiC power MOSFETs have transitioned from being a research exercise to becoming an industrial reality. The potential benefits that can be drawn from this technology in the electrical energy conversion domain have been amply discussed and partly demonstrated. Before their widespread use in the field, the transistors need to be thoroughly investigated and later validated for robustness and longer term stability and reliability. This paper proposes a review of commercial SiC power MOSFETs state-of-the-art characteristics and discusses trends and needs for further technology improvements, as well as device design and engineering advancements to meet the increasing demands of power electronics

A Brief Overview of SiC MOSFET Failure Modes and Design Reliability

This paper briefly introduces various aspects which should be considered when implementing Silicon Carbide (SiC) based metal-oxide-semiconductor-field-effect-transistors (MOSFETs) into a design. There is an increasing trend regarding the use of these devices in various applications due to their improved performance over conventional Silicon (Si) based devices. The failure modes of SiC MOSFETs are discussed, as well as the indicators which signal device degradation and failure. The impact of packing design on reliability and performance is also discussed along with a number of application related concepts which bring to light some of the issues regarding the use of SiC MOSFETs as a relatively young technology

Single pulse avalanche robustness and repetitive stress ageing of SiC power MOSFETs

This paper presents an extensive electro-thermal characterisation of latest generation silicon carbide (SiC) Power MOSFETs under unclamped inductive switching (UIS) conditions. Tests are carried out to thoroughly understand the single pulse avalanche ruggedness limits of commercial SiC MOSFETs and assess their aging under repetitive stress conditions. Both a functional and a structural characterisation of the transistors is presented, with the aim of informing future device technology development for robust and reliable power system development

Study of Silicon Carbide Power MOSFETs Behaviour in Out-of-SOA Conditions

The need for efficient conversion and control of electrical power in many application areas has rapidly increased the demand for power devices with better and better performances. In order to go beyond the limit imposed by Silicon devices, there has always been a great interest for new materials. In recent years, Silicon Carbide Power devices, mainly power diodes and MOSFETs, have become commercially available and have begun to replace their Silicon counterpart in many application areas. The reason lays in some superior material properties that allow developing higher efficient power systems. Nevertheless, a wider spread of these devices could not be achieved without a deep analysis of the elements that might affect their reliability. The current work deals with the study of SiC Power MOSFETs reliability, with particular focus on short-circuit operation. To achieve this purpose, wide set of experiments has been carried out on commercially available devices, providing both electrical and thermal characterization. Alongside experimental evidences, TCAD simulations have been used to get a full understanding of the inner physical failure dynamics. Eventually, it has been possible to give explanation about SiC Power MOSFETs failure mechanisms. In particular, two different phenomena might occur and both are related to temperature increase inside the device

Performance and robustness characterisation of SiC power MOSFETs

Over the last few years, significant advancements in the SiC power MOSFET fabrication technology has led to their wide commercial availability from various manufacturers. As a result, they have now transitioned from being a research activity to becoming an industrial reality. SiC power MOSFET technology offers great benefits in the electrical energy conversion domain which have been widely discussed and partially demonstrated. Superior material properties of SiC and the consequent advantages are both later discussed here. For any new device technology to be widely implemented in power electronics applications, it’s crucial to thoroughly investigate and then validate for robustness, reliability and electrical parameter stability requirements set by the industry. This thesis focuses on device characterisation of state-of-the-art SiC power MOSFETs from different manufacturers during short circuit and avalanche breakdown operation modes under a wide range of operating conditions. The functional characterisation of packaged DUTs was thoroughly performed outside of the safe operating area up until failure test conditions to obtain absolute device limitations. For structural characterisation, Infrared thermography on bare die DUTs was also performed with an aim to observe hotspots and/or degradation of the structural features of the device. The experimental results are also complemented by 2D TCAD simulation results in order to get a further insight into the underlying physical mechanisms behind failure during such operation regimes. Moreover, the DUTs were also tested for body diode characterisation with an aim to observe degradation and instability of electrical device parameters which may adversely affect the performance of the overall system. Such investigations are really important and act as a feedback to device manufacturers for further technological improvements in order to overcome the highlighted issues with an aim to bring about advancements in device design to meet the ever-increasing demands of power electronics

SiC MOSFET and GaN FET in high voltage switching applications

For several decades, silicon-based semiconductor devices, such as Si MOSFETs have been the main choice for switching applications. However, their level of performance is approaching its maximum potential, and further development becomes increasingly challenging. As a result, semiconductor manufacturers and the electronics industry are exploring new technologies to meet current requirements. One promising option is the use of WBG (Wide Band Gap) devices, such as GaN FETs and SiC MOSFETs, which have gained attention due to their superior performance characteristics. Compared to traditional Si transistors, WBG devices can withstand higher voltages and tem-peratures, are faster, can be packed in smaller sizes, and are more efficient. This study aims to serve as a guide for designers seeking information on the technology and usage of WBG transistors, particularly in high voltage switching applications. The study in-cludes an examination of the structures of SiC MOSFETs and GaN FETs, as well as their most important electrical characteristics. Additionally, the efficiency of an LCC converter was measured to compare the performance of various FET types, with a specific interest in the use of WBG devices in soft switching applications. Scientific articles, application notes, and datasheets were investigated to provide a thorough understanding of the theory behind SiC MOSFETs and GaN FETs. According to resources, the primary SiC MOSFET and GaN FET technologies suitable for high voltage switching are planar SiC MOSFET, trench SiC MOSFET, p-GaN FET and GaN/Si cascode transistor. These devices are currently available with breakdown voltages of 1700 V (planar SiC MOSFET), 2000 V (trench SiC MOSFET), 650 V (p-GaN FET) and 900 V (GaN/Si cascode transistor). The efficiency of an LCC converter with a maximum output power of 40 W was measured using 1500 V Si MOSFET, 1700 V planar SiC MOSFET, 1700 V trench SiC MOSFET, and 900 V GaN/Si cascode transistor. A constant load of 1 A was used, and the input voltage was incre-mentally increased from 300 V to 900 V in 100 V steps. According to results, using planar and trench SiC MOSFETs, LCC converter had the highest efficiency, reaching up to 89,6 % while Si MOSFET exhibited slightly lower efficiency, which was 87,7 % at its best. GaN/Si cascode tran-sistors showed comparable efficiency to SiC MOSFETs at lower input voltages but fell signifi-cantly behind as the voltage increased, having eventually much worse efficiency than Si MOSFET.Useiden vuosikymmenien ajan pii-pohjaiset puolijohteet, kuten pii MOSFETit, ovat olleet pääasiallinen teknologia katkojasovelluksissa. Niiden suorituskyky lähestyy kuitenkin ylärajaa, ja niiden kehittäminen käy yhä vaikeammaksi. Tämän vuoksi puolijohdevalmistajat ja elektroniikkateollisuus etsivät uusia teknologioita täyttää nykyiset vaatimukset. Yksi lupaava teknologia ovat laajan energiavyön puolijohteet, kuten galliumnitridi FETit ja piikarbidi MOSFETit. Viime vuosina ne ovat herättäneet paljon huomiota niiden ylivoimaisten ominaisuuksien vuoksi. Verrattuna perinteisiin pii MOSFETeihin, laajan energiavyön transistorit kestävät suurempia jännitteitä ja lämpötiloja, ovat nopeampia ja ne voidaan pakata pienempään kokoon. Lisäksi ne ovat tehokkaampia. Tämä diplomityö pyrkii toimimaan oppaana elektroniikkasuunnittelijoille, jotka etsivät tietoa laajan energiavyön transistoreista ja niiden käytöstä erityisesti suurjännitekatkojasovelluksissa.Työssä tarkastellaan piikarbidi MOSFETien ja galliumnitridi FETien rakenteita sekä niiden tärkeimpiä sähköisiä ominaisuuksia. Lisäksi mitattiin kelaan ja kahteen kondensaattoriin perustuvan LCC resonanssiteholähteen hyötysuhde eri FET-tyypeillä, koska haluttiin saada tietoa laajan energiavyön transistorien käytöstä pehmeässä jännitteen katkonnassa. Tiedon keräämiseksi tutkittiin tieteellisiä artikkeleita, sovellusohjeita ja datalehtiä. Lähdeaineiston perusteella pääasialliset piikarbidi MOSFETien ja galliumnitridi FETien teknologiat suurjännitesovellusten alueella ovat planaarinen piikarbidi MOSFET, erityiseen kaivanto teknologiaan (trench) perustuva piikarbidi MOSFET, p-tyypin galliumnitridi FET ja galliumnitridi/pii kaskadi transistori. Tällä hetkellä näitä teknologioita on kaupallisesti saatavilla enimmillään 1700 V (planaarinen piikarbidi MOSFET), 2000 V (kaivanto piikarbidi MOSFET), 650 V (p-tyypin galliumnitridi FET) ja 900 V (galliumnitridi/pii kaskadi transistori) jännitteillä. Nimellisteholtaan 40 W LCC resonanssi teholähteen hyötysuhde mitattiin 1500 V pii MOSFETeilla, 1700 V planaarisilla piikarbidi MOSFETeilla, 1700 V kaivanto piikarbidi MOSFETeilla ja 900 V gallium-nitridi/pii kaskadi transistoreilla. Kuormana käytettiin 1 A vakiokuormaa ja tulojännitettä nostettiin asteittain 300 voltista 900 voltiin 100 voltin nostoin. Tulosten mukaan paras hyötysuhde oli 89,6 %, joka mitattiin planaarisella piikarbidi MOSFETilla ja kaivanto piikarbidi MOSFETilla. Pii MOSFETien tapauksessa hyötysuhde oli hieman huonompi, ollen parhaimmillaan 87,7 %. Alhaisilla jännitteillä galliumnitridi/pii kaskadi transistorien hyötysuhde oli verrattavissa piikarbidi MOSFETeihin, mutta hyötysuhde laski jännitettä nostettaessa, ollen lopulta merkittävästi huonompi kuin pii MOSFETeilla

Characterization and Modeling of the Threshold Voltage Instability in p-Gate GaN HEMTs

The p-gate GaN HEMT is a modern power semiconductor transistor capable of overcoming the switching speed limitation of conventional Silicon-based technologies. However, the GaN HEMT is a fairly new technology that still suffers undesired effects that affect its operation. Nowadays, the most prominent effects are the shift and instability of the threshold voltage Vth, caused by capacitive coupling into the gate stack as well as trapping, accumulation, and depletion of carriers. In this study, an experimental characterization of the Vth behavior is executed and subsequently used to develop a physically-based compact model. For this purpose, a custom setup is developed capable of high-resolution transient measurements for pulse lengths ranging from 100 ns up to 100 s. Utilizing the setup, commercially available state-of-the-art p-gate GaN HEMTs are investigated, showing a Vth shift and instability that appears relevant up to the nominal operation. The experimental results show that the drain-source voltage VDS yields a Vth shift, which, when applied for long durations (e.g., during off-state), leads to an additional Vth instability. The gate-source voltage VGS also yields significant Vth instabilities, which correlate with the VDS-induced effects. Furthermore, the driving conditions causing an impact on Vth appear to also correlate with the devices’ short-circuit capability and degradation. However, no available models cover the Vth behavior, which is necessary to predict their impact and reliability concerns. Consequently, a compact model is developed based on the surface potential for the drain path, extended by the conduction mechanisms covering the gate path. Finally, the Vth shift is modeled based on capacitive coupling into the gate, while for the Vth instabilities, a possible implementation is exemplified for the impact of VDS