HIGH FREQUENCY COMMON-MODE NOISE IN SERDES CIRCUITS’ OPTIMIZED INTERCONNECTIONS

According to the requirements imposed by the new four-level pulse amplitude modulation (PAM4) standard for high-speed data transfer and processing, electrical constraints and manufacturing tolerances in integrated electronic packages impose accurate electromagnetic simulations and new S-parameters analysis, saving time and financial resources for next-generation switches, routers or data centers circuits implementation. The complexity of the advanced networking class circuits’ encapsulation substrates massively increases due to the large number of differential signals that it integrates. Differential signaling has replaced single-ended transmission in high-speed circuits due to their many advantages, including increased immunity to crosstalk and electromagnetic interference, but common-mode noise due to timing skew or amplitude unbalance differences can still affect them. This work tests five different models, identifies and optimizes the 45° bends, structures that commonly affect the reflections in a differential stripline. Then it studies differential transmission lines in stripline topology, implemented in a 12-layered flip-chip package, using S-parameters, inspecting and comparing the common-mode noise. In this way, the paper combines microwave theory with a real chip packaging design in an innovative way, using finite element analysis of electromagnetic field simulation and mixed-mod scattering parameters of differential topologies, towards an optimized structure design

The Development of Novel Interconnection Technologies for 3D Packaging of Wire Bondless Silicon Carbide Power Modules

This dissertation advances the cause for the 3D packaging and integration of silicon carbide power modules. 3D wire bondless approaches adopted for enhancing the performance of silicon power modules were surveyed, and their merits were assessed to serve as a vision for the future of SiC power packaging. Current efforts pursuing 3D wire bondless SiC power modules were investigated, and the concept for a novel SiC power module was discussed. This highly-integrated SiC power module was assessed for feasibility, with a focus on achieving ultralow parasitic inductances in the critical switching loops. This will enable higher switching frequencies, leading to a reduction in the size of the passive devices in the system and resulting in systems with lower weight and volume. The proposed concept yielded an order-of-magnitude reduction in system parasitics, alongside the possibility of a compact system integration. The technological barriers to realizing these concepts were identified, and solutions for novel interconnection schemes were proposed and evaluated. A novel sintered silver preform was developed to facilitate flip-chip interconnections for a bare-die power device while operating in a high ambient temperature. The preform was demonstrated to have 3.75× more bonding strength than a conventional sintered silver bond and passed rigorous thermal shock tests. A chip-scale and flip-chip capable power device was also developed. The novel package combined the ease of assembly of a discrete device with a performance exceeding a wire bonded module. It occupied a 14× smaller footprint than a discrete device, and offered power loop inductances which were less than a third of a conventional wire bonded module. A detailed manufacturing process flow and qualification is included in this dissertation. These novel devices were implemented in various electrical systems—a discrete Schottky barrier diode package, a half-bridge module with external gate drive, and finally a half-bridge with integrated gate driver in-module. The results of these investigations have been reported and their benefits assessed. The wire bondless modules showed \u3c 5% overshoot under all test conditions. No observable detrimental effects due to dv/dt were observed for any of the modules even under aggressive voltage slew rates of 20-25 V/ns

94 GHz Monolithic Transmitter for Weather Radar Application

This thesis was written for concluding my studies at the University of Padua. The main topic is the design of a monolithic transmitter in SiGe bipolar technology, for weather radar application at an operating frequency around 94GHz. At such a high frequency parasitic elements have to be taken into account very carefully. Appropriate matching networks become important to allow the signals to pass across the different ections of the transmitter, without reflections or attenuations. To this aim, transmission lines were used instead of inductors, in order to save size and to have a more reliable modelling of device parameters and parasitic elements. The structure of the transmitter includes a transformer (which acts as Balun), a frequency quadrupler and a buffer. The transmitter input receives a single-ended reference signal at 23.5GHz, with a power of 0dBm on a single-ended input impedance of 50Ω. The output has been designed for a differential load of 100Ω and to operate in the temperature range of 0°C - 100°C, with a typical output power above 10dBm and spurious harmonic below -25dBcopenMotivi di sicurezza e/o proprietà dei risultati e/o informazioni sensibil

Multi-chip module interconnections at microwave frequencies: electromagnetic simulation and material characterisation

In this work both the interconnections and materials used in multi-chip modules (MCMs) at microwave frequencies have been investigated. The electrical behaviour of the interconnections was studied using commercially available 2.SD and 3D electromagnetic simulators (HFSSTM, MDSTM and Momentum™). State-of-the-art conductive and dielectric film materials used in the fabrication of multi-layer MCM structures were characterized using microstrip/wave guide resonator techniques. The models chosen for simulation of interconnections are commensurate with those in current use in MCM technology. Crosstalk between microstrip conductors in multi-layer MCM structures was simulated and new knowledge leading to new design rules was obtained.Typical elements in MCM interconnect structures, such as vias, bends and airbridges were also investigated. The principal features of these elements were simulated and the results were obtained in S-parameter form. Based on the simulated results, these parasitic elements were modelled in terms of their equivalent circuits which can be used in circuit simulators to aid more rigorous MCM circuit design. A microstrip ring resonator, fabricated using the newly developed conductive material from Heraeus, was employed to measure the line loss. New techniques have been developed to measure the permittivity and loss tangent of thin dielectric films. In the previous methods for the measurement of these films, the accuracy in measuring the relative permittivity is limited and there is no available technique to measure the loss tangent. A novel cavity perturbation method was developed to accurately measure both the relative permittivity and loss tangent of the films deposited on a supporting substrate. An additional independent technique, derived from transmission line theory, for measuring the relative permittivity of dielectric film was also established. A particular feature of the new teclmiques, which led to high accuracy in measuring dielectric constant and loss tangent was the positioning of the dielectric film in the region of maximum electric field strength, thereby ensuring maximum interaction between the electric field and the film material. A rigorous error analysis was performed on the new techniques, which led to the establishment of practical measurement correction factors. A simple and rigorous method has also been developed to accurately measure the loss tangent of dielectrics with known dielectric constant using a resonant cavity. The novel method eliminates the need for any physical measurement of the dielectric sample. The new technique should permit the development of techniques for very high frequency characterisation of dielectric materials

Modelling and analysis of crosstalk in scaled CMOS interconnects

The development of a general coupled RLC interconnect model for simulating scaled bus structures m VLSI is presented. Several different methods for extracting submicron resistance, inductance and capacitance parameters are documented. Realistic scaling dimensions for deep submicron design rules are derived and used within the model. Deep submicron HSPICE device models are derived through the use of constant-voltage scaling theory on existing 0.75µm and 1.0µm models to create accurate interconnect bus drivers. This complete model is then used to analyse crosstalk noise and delay effects on multiple scaling levels to determine the dependence of crosstalk on scaling level. Using this data, layout techniques and processing methods are suggested to reduce crosstalk in system

Characterization and electrical circuit modeling of interconnections and packages using time domain network analysis

The improved accuracy of Time Domain Reflection and Transmission (TDR/T) measurements made possible by the calibration process known as Time Domain Network Analysis (TDNA) is applied to the problem of characterization and modeling of electronic interconnect and packaging structures. TDNA uses measurements of known and partially known calibration standards to characterize the measurement system allowing for the correction of the raw measurements of an unknown network to eliminate the effects of system non-idealities and resulting in a significant improvement of the measurement quality. The correction process is shown to be analogous to the well established Frequency Domain Vector Network Analyzer calibrations and to have the same capabilities for high precision metrology applications. Methods are developed to extract electrical circuit models from time domain measurements of lossless, nonuniform, multiconductor transmission lines for two broad classes of structures. Although unique solutions are not feasible for general structures that scatter the propagating wave-front, approximate solutions have been identified using the assumption of a single velocity wave-front, the case for homogeneous media. For structures with identical lines, such as a parallel line bus structure, the propagation behavior (eigenvector matrix) is determined only by the number of conductors, N, and is therefore known a priori for the entire structure allowing decoupling of the system into N orthogonal nonuniform transmission lines. Circuit models have been developed for these decoupled nonuniform lines as well as for the equal modal velocity assumption which relies on a matrix impedance profile to fully describe the system. The implications of non-ideal grounding of interconnection circuits is explored. Traditional lumped element methods for modeling these effects are examined and typical examples where distributed circuit models are necessary to adequately describe the system are identified. Techniques for examining power-planes and substrate connections in integrated circuits and integrated circuit packages using the distributed ground model are presented. Novel circuit design methods to circumvent the limitations imposed by non-ideal grounds and nonzero length transmission structures are also proposed

Analysis of Parasitic Oscillations in Commutation Cells with High Voltage Power MOSFETs

The dynamic behavior of power semiconductor devices with decreasing area-specic on resistances is more and more inf uenced by parasitic characteristics of packages and PCBs. These parasitic characteristics can increase the switching times of power semiconductors andhence reduce the efficiency of power electronic circuits. Furthermore, during commutation the reliability of circuits can be compromised by parasitic oscillations with temporarily increasing amplitudes. Optimized parasitic characteristics of packages and PCBs are thereforenecessary. This applies in particular, if fast power semiconductors are used. Using the example of a one quadrant buck converter topology with a high voltage power MOSFET and a SiC Schottky diode, in this work a methodology is developed that enables the predictionof parasitic oscillations with temporarily increasing amplitudes during commutation and the improvement of the stability of commutation cells. Thereto, suitable circuit models of the power semiconductors and the semiconductor's environment are required. Large-signal models of power MOSFETs and Schottky diodes are deduced for the relevant operating conditions. The combination of curve tracer and short circuit measurements allows the static parameterization of the MOSFET model for the regarded operating range. It is shown that the MOSFET's capacitances can be determined from dynamic measurements. Compared to capacitances measured in accordance with DIN ICE 747, the dynamic capacitances result in an improved conformity of simulations and measurements. The parasitic characteristics of the PCB and packages are modeled with coupling capacitances and effective resistances and inductances. The parameterization of the model is based on quasi-static field simulations of the 3D models of the PCB and packages. The derived behavioral models of the power semiconductors and the electrical interconnections of the PCB and packages are combined with simple models of the DC voltage link, the driver and the load circuit to the model of the buck converter topology. The comparison of measured and simulated switching characteristics approves the proposed buck converter model and the determined parameterization. For the relevant operating points of the buck converter topology, small-signal equivalent circuit models are deduced. It is shown that the stability analysis of the small-signal models enables the prediction of parasitic oscillations with temporarily increasing oscillations during commutation. From the stability analysis of the small-signal models with different parameterizations, measures for an improved stability of the commutation cell are concluded. Design iterations and development costs can be saved with the presented methodology.Das dynamische Verhalten von Leistungshalbleitern mit immer kleineren flächenspezifischen Einschaltwiderständen wird stärker durch die parasitären Eigenschaften von Gehäusen und Leiterplatten beeinflusst. So können die Parasiten die Schaltzeiten der Halbleiter erhöhen und damit die Effizienz von leistungselektronischen Schaltungen verringern. Außerdem kann die Zuverlässigkeit von Schaltungen während der Kommutierung durch parasitäre Schwingungen mit zwischenzeitlich steigenden Amplituden beeinträchtigt werden. Insbesondere bei Verwendung von schnellen Leistungshalbleitern ist deshalb die Optimierung der parasitären Eigenschaften von Gehäusen und Leiterplatten notwendig. Am Beispiel eines Tiefsetzstellers mit einem Hochvolt-Leistungs-MOSFET und einer SiC Schottky-Diode wird in dieser Arbeit eine Methodik entwickelt, die die Vorhersage von parasitären Schwingungen mit zwischenzeitlich steigenden Amplituden während der Kommutierung und die Stabilitätsoptimierung von Kommutierungszellen ermöglicht. Dafür werden geeignete Modelle der Leistungshalbleiter und der Halbleiterumgebung benötigt. Verhaltensmodelle von Leistungs-MOSFETs und Schottky-Dioden werden für die relevanten Betriebsbedingungen abgeleitet. Die Kombination von Curve-Tracer- und Kurzschlussmessungen ermöglicht die statische Parametrierung des MOSFET-Models für den betrachteten Betriebsbereich. Es wird gezeigt, dass die Kapazitäten des MOSFET-Models aus dynamischen Messungen extrahiert werden können und dass diese Kapazitäten zu einer besseren Übereinstimmung von Messungen und Simulationen führen als die Kapazitäten, die entsprechend der DIN IEC 747 gemessen wurden. Die parasitären Eigenschaften von Gehäusen und Leiterplatten werden mit Koppelkapazitäten und effektiven Widerständen und Induktivitäten modelliert. Mit Hilfe der Finite-Elemente- und der Randelemente-Methode werden die Modellparameter bestimmt. Die entwickelten Verhaltensmodelle der Halbleiter und der elektrischen Verbindungen sowie einfache Modelle des Zwischen-, Treiber- und Lastkreises werden zum Modell des Tiefsetzstellers zusammengefügt. Das Modell kann mit den gemessenen bzw. berechneten Kennlinienfeldern und Parametern das Schaltverhalten des MOSFETs nachbilden. Für die relevanten Arbeitspunkte des Tiefsetzstellers werden Kleinsignalersatzschaltbilder ermittelt. Es wird gezeigt, dass die Stabilitätsanalyse der Kleinsignalersatzschaltbilder die Vorhersage von parasitären Schwingungen mit zwischenzeitlich steigenden Amplituden während der Kommutierung ermöglicht. Maßnahmen zur Stabilitätsoptimierung der Kommutierungszelle werden aus den Ergebnissen der Stabilitätsanalyse von verschiedenen Parametrierungen abgeleitet. Designiterationen und Entwicklungskosten können so reduziert werden.Auch im Buchhandel erhältlich: Analysis of Parasitic Oscillations in Commutation Cells with High Voltage Power MOSFETs / Vera van Treek Ilmenau : ISLE 2014. - xiii, 237 S. ISBN 978-3-938843-79-