PGPG: An Automatic Generator of Pipeline Design for Programmable GRAPE Systems

We have developed PGPG (Pipeline Generator for Programmable GRAPE), a software which generates the low-level design of the pipeline processor and communication software for FPGA-based computing engines (FBCEs). An FBCE typically consists of one or multiple FPGA (Field-Programmable Gate Array) chips and local memory. Here, the term "Field-Programmable" means that one can rewrite the logic implemented to the chip after the hardware is completed, and therefore a single FBCE can be used for calculation of various functions, for example pipeline processors for gravity, SPH interaction, or image processing. The main problem with FBCEs is that the user need to develop the detailed hardware design for the processor to be implemented to FPGA chips. In addition, she or he has to write the control logic for the processor, communication and data conversion library on the host processor, and application program which uses the developed processor. These require detailed knowledge of hardware design, a hardware description language such as VHDL, the operating system and the application, and amount of human work is huge. A relatively simple design would require 1 person-year or more. The PGPG software generates all necessary design descriptions, except for the application software itself, from a high-level design description of the pipeline processor in the PGPG language. The PGPG language is a simple language, specialized to the description of pipeline processors. Thus, the design of pipeline processor in PGPG language is much easier than the traditional design. For real applications such as the pipeline for gravitational interaction, the pipeline processor generated by PGPG achieved the performance similar to that of hand-written code. In this paper we present a detailed description of PGPG version 1.0.Comment: 24 pages, 6 figures, accepted PASJ 2005 July 2

Configurable Verification of RISC Processors

The Verification methodology of modern processor designs is an enormous challenge. As processor design complexity increases, an elaborate and sophisticated verification environment has to be employed to identify, assist in debug, and document design bugs. This paper presents a configurable verification environment for RISC processors. The verification environment is developed in SystemVerilog, an IEEE standard that bridges the gap between design and verification by delivering a single language and environment for both. The verification environment will validate the performance of the RISC processors with a micro-architectural model developed in SystemC. The system also comprises of an intelligent Instruction Generator that generates random sequences of instructions. All verification system components are configured using a common RISC processor architecture configuration control file

Microprocessor system IP core generator

Diplomová práce se týká programovacího jazyku VHDL, návrhového systému ISE Webpack a mikroprocesoru PicoBlaze. Popisuje základy jazyka VHDL a jeho použití. Dále je v práci popsán způsob práce s programem ISE Webpack. V práci jsou popsány nejběžnější periferie a je zde popsán také Picoblaze procesor s jeho parametry a realizace. Na konec je zde popsán IP generátor pro generaci komplexního FPGA návrhu s procesorem Picoblaze.This master’s thesis deal’s with VHDL programming language, ISE Webpack design system and PicoBlaze microprocessor. The thesis describes essentials of VHDL programming language and its application. A simple introduction to ISE Webpack design environment is given. The thesis describes common peripherals and the PicoBlaze processor is described too, including its parameters and implementation aspects. Finally the thesis describes IP generator for generating complex FPGA design including Picoblaze processor.

XAGra - an XML dialect for attribute grammars

Attribute Grammars (AG) are a powerful and well-known formalism used to create language processors. The meta-language used to write an AG (to specify a language and its processor) depends on the compiler generator tool chosen. This fact can be an handicap when it is necessary to share or transfer information between language-based systems; this is, we face an interchangeability problem, if we want to reuse the same language specification (the AG) on another development environment. To overcome this interoperability flaw, we present in this paper XAGra - an XML dialect to describe attribute grammars. XAGra was precisely conceived aiming at adapting the output of a visual attribute grammar editor (named VisualLISA) to any compiler generator tool. Based on the formal definition of Attribute Grammar and on the usual requirements for the generation of a language processor, XAGra schema is divided into five main fragments: symbol declarations, attribute declarations, semantic productions (including attribute evaluation rules, contextual conditions, and translation rules), import, and auxiliary functions definitions. In the paper we present those components, but the focus will be on the systematic way we followed to design the XML schema based on the formal definition of AG. To strength the usefulness of XAGra as a universal AG specification, we show at a glance XAGraAl, a tool taking as input an AG written in XAGra, is a Grammar Analyzer and Transformation system that computes dependencies among symbols, various metrics, slices and rebuilds the grammar

COBOL report program generation by macro processor

The research described is directed towards the development of an interactive COBOL program generator. This aims to simplify computer usage and contribute to the more effective use of computer resources, by alleviating the burdensome, time-consuming and error-prone activity of programming. The work is based on PG/1, an existing macro processor, and in particular considers the generation of report programs. The problems of program generation by macro processor are first explored using Filetab, an existing report specification language,' and avoiding the interactive aspect. This establishes the feasibility of generating COBOL programs but identifies shortcomings in the macro processor facilities. Enhancements to the macro processor are defined and the PG/2 version is created for use. The development of an interactive self-instructional COBOL report program generator for the casual user is chosen as the area for deeper investigation. From a consideration of data bases and query languages it is concluded that a relational view of the data forms the most natural basis for a computer-dominated, non-procedural report-specifying dialogue with a casual user. A design study for an interactive self-teaching COBOL report program generator^ based on the PG/2 macro processor and offering some of the benefits of a Relational Data base Management System, is described. The validation of the user's responses is a major undertaking and leads to a large system. Details of the macros implementing selected features are presented. It is concluded that program generation appears efficient but may be of even greater use to a professional programmer than to the non-specialist user. The PG/2 macro processor, although not an ideal tool for COBOL program generation, serves to identify the characteristics of an appropriate tool. There is potential for extending and adapting the techniques used to other applications

An Ada programming support environment

The toolset of an Ada Programming Support Environment (APSE) being developed at North American Aircraft Operations (NAAO) of Rockwell International, is described. The APSE is resident on three different hosts and must support developments for the hosts and for embedded targets. Tools and developed software must be freely portable between the hosts. The toolset includes the usual editors, compilers, linkers, debuggers, configuration magnagers, and documentation tools. Generally, these are being supplied by the host computer vendors. Other tools, for example, pretty printer, cross referencer, compilation order tool, and management tools were obtained from public-domain sources, are implemented in Ada and are being ported to the hosts. Several tools being implemented in-house are of interest, these include an Ada Design Language processor based on compilable Ada. A Standalone Test Environment Generator facilitates test tool construction and partially automates unit level testing. A Code Auditor/Static Analyzer permits the Ada programs to be evaluated against measures of quality. An Ada Comment Box Generator partially automates generation of header comment boxes

The language parallel Pascal and other aspects of the massively parallel processor

A high level language for the Massively Parallel Processor (MPP) was designed. This language, called Parallel Pascal, is described in detail. A description of the language design, a description of the intermediate language, Parallel P-Code, and details for the MPP implementation are included. Formal descriptions of Parallel Pascal and Parallel P-Code are given. A compiler was developed which converts programs in Parallel Pascal into the intermediate Parallel P-Code language. The code generator to complete the compiler for the MPP is being developed independently. A Parallel Pascal to Pascal translator was also developed. The architecture design for a VLSI version of the MPP was completed with a description of fault tolerant interconnection networks. The memory arrangement aspects of the MPP are discussed and a survey of other high level languages is given

Design and implementation of an asynchronous version of the MIPS R3000 microprocessor

The goal of this thesis is to demonstrate the feasibility of converting a synchronous general purpose microprocessor design to one using an asynchronous methodology. This thesis is one of three parts that details the entire design of an asynchronous version of the MIPS R3000 microprocessor. The design excludes all of the memory support features of the processor for two reasons. First, the memory is already handled asynchronously and second, the size of the project must be limited. This design has implemented the entire set of instructions from the original synchronous version with the exception of certain memory instructions. The three participants in this project are Paul Fanelli, Kevin Johnson, and Scott Siers. Paul Fanelli has developed a Very High Speed Integrated Circuit Hardware Description Language (VHDL) model for the processor. Kevin Johnson has designed the register bank, arithmetic logic unit, and shifter, including schematic diagrams and layouts. Scott Siers has designed the pipeline stages, the multiplier/divider, the exception handler, and the completion signal generator, including schematic diagrams and layout. Each of the participants has written a separate thesis that covers one part of the total design

The use of model-checking for the verification of concurrent algorithms

The design of concurrent algorithms tends to be a long and difficult process. Increasing the number of concurrent entities to realistic numbers makes manual verification of these algorithms almost impossible. Designers normally resort to running these algorithms exhaustively yet can never be guaranteed of their correctness. In this report, we propose the use of a model-checker (SMV) as a machine-automated tool for the verification of these algorithms. We present methods how this tool can be used to encode algorithms and allow properties to be guaranteed for uni-processor machines running a scheduler or SMP machines. We also present a language-generator allowing the designer to use a description language that is then automatically converted to the model-checker’s native language. We show how this approach was successful in encoding a concurrent algorithm and is able to verify the desired properties.peer-reviewe

A finite element based design tool for point fixed laminated glass

In this master’s project, a design tool for bolt fixed laminated glass was developed, based on linear-elastic finite element theory. The program produces images of the deflections and stress distributions in bolted glass panes. A two-dimensional triangular mesh, created by an external mesh generator, was extended to a three-dimensional mesh comprising 15-node wedge elements. A least-square method was adopted for extrapolating stresses from Gaussian sample points to the element nodes. A simple graphical user interface was developed in the programming language Python, as well as a simple post-processor employing the graphics library OpenGL