The goal of this thesis is to demonstrate the feasibility of converting a synchronous general purpose microprocessor design to one using an asynchronous methodology. This thesis is one of three parts that details the entire design of an asynchronous version of the MIPS R3000 microprocessor. The design excludes all of the memory support features of the processor for two reasons. First, the memory is already handled asynchronously and second, the size of the project must be limited. This design has implemented the entire set of instructions from the original synchronous version with the exception of certain memory instructions. The three participants in this project are Paul Fanelli, Kevin Johnson, and Scott Siers. Paul Fanelli has developed a Very High Speed Integrated Circuit Hardware Description Language (VHDL) model for the processor. Kevin Johnson has designed the register bank, arithmetic logic unit, and shifter, including schematic diagrams and layouts. Scott Siers has designed the pipeline stages, the multiplier/divider, the exception handler, and the completion signal generator, including schematic diagrams and layout. Each of the participants has written a separate thesis that covers one part of the total design
