The Verification methodology of modern processor designs is an enormous challenge. As processor design complexity increases, an elaborate and sophisticated verification environment has to be employed to identify, assist in debug, and document design bugs. This paper presents a configurable verification environment for RISC processors. The verification environment is developed in SystemVerilog, an IEEE standard that bridges the gap between design and verification by delivering a single language and environment for both. The verification environment will validate the performance of the RISC processors with a micro-architectural model developed in SystemC. The system also comprises of an intelligent Instruction Generator that generates random sequences of instructions. All verification system components are configured using a common RISC processor architecture configuration control file
