430,269 research outputs found
HD 181068: A Red Giant in a Triply-Eclipsing Compact Hierarchical Triple System
Hierarchical triple systems comprise a close binary and a more distant
component. They are important for testing theories of star formation and of
stellar evolution in the presence of nearby companions. We obtained 218 days of
Kepler photometry of HD 181068 (magnitude of 7.1), supplemented by groundbased
spectroscopy and interferometry, which show it to be a hierarchical triple with
two types of mutual eclipses. The primary is a red giant that is in a 45-day
orbit with a pair of red dwarfs in a close 0.9-day orbit. The red giant shows
evidence for tidally-induced oscillations that are driven by the orbital motion
of the close pair. HD 181068 is an ideal target for studies of dynamical
evolution and testing tidal friction theories in hierarchical triple systems.Comment: 22 pages, including supporting on-line material. This is the author's
version of the work. It is posted here by permission of the AAAS for personal
use, not for redistribution. The definitive version was published in Science
Vol. 332 no. 6026 pp. 216-218 (8 April 2011), doi:10.1126/science.1201762.
http://www.sciencemag.org/content/332/6026/216.ful
A LVDS Serial AER Link
Address-Event-Representation (AER) is a
communication protocol for transferring asynchronous events
between VLSI chips, originally developed for bio-inspired
processing systems (for example, image processing). Such
systems may consist of a complicated hierarchical structure
with many chips that transmit data among them in real time,
while performing some processing (for example, convolutions).
The event information is transferred using a high speed digital
parallel bus (typically 16 bits and 20ns-40ns per event). This
paper presents a testing platform for AER systems that allows
to analyse a LVDS Serial AER link. The interface allows up to
0.7 Gbps (~40Mev/s, 16 bits/ev). The eye diagram ensures that
the platform could support 1.2 Gbps.Commission of the European Communities IST-2001-34124 (CAVIAR)Comisión Interministerial de Ciencia y Tecnología TIC-2003-08164-C03-0
LVDS Serial AER Link performance
Address-Event-Representation (AER) is a
communication protocol for transferring asynchronous events
between VLSI chips, originally developed for bio-inspired
processing systems (for example, image processing). Such
systems may consist of a complicated hierarchical structure
with many chips that transmit data among them in real time,
while performing some processing (for example, convolutions).
The event information is transferred using a high speed digital
parallel bus (typically 16 bits and 20ns-40ns per event). This
paper presents a testing platform for AER systems that allows
analysing a LVDS Serial AER link produced by a Spartan 3
FPGA, or by a commercial LVDS transceiver. The interface
allows up to 0.728 Gbps (~40Mev/s, 16 bits/ev). The eye
diagram ensures that the platform could support 1.2 Gbps.Commission of the European Communities IST-2001-34124 (CAVIAR)Comisión Interministerial de Ciencia y Tecnología TIC-2003-08164-C03-0
Performance Evaluation of Hierarchical Simulation Systems
Simulation needs for design analysis, verification, and testing have become increasingly important as integrated circuit size and complexity have grown. One technique for dealing with this problem is to utilize hierarchical modeling and simulation methods. This paper presents an analysis of hierarchical simulation systems in terms of two performance measures; the number of statements required for describing a system, and the simulation system execution time associated with a given hierarchical system representation. A model of hierarchical simulation system performance is developed. The performance of the hierarchical simulator, lsim2, is examined through its use on the set of benchmark circuits and the results discussed in light of model predictions
Requirements for implementing real-time control functional modules on a hierarchical parallel pipelined system
Analysis of a robot control system leads to a broad range of processing requirements. One fundamental requirement of a robot control system is the necessity of a microcomputer system in order to provide sufficient processing capability.The use of multiple processors in a parallel architecture is beneficial for a number of reasons, including better cost performance, modular growth, increased reliability through replication, and flexibility for testing alternate control strategies via different partitioning. A survey of the progression from low level control synchronizing primitives to higher level communication tools is presented. The system communication and control mechanisms of existing robot control systems are compared to the hierarchical control model. The impact of this design methodology on the current robot control systems is explored
A Route Confidence Evaluation Method for Reliable Hierarchical Text Categorization
Hierarchical Text Categorization (HTC) is becoming increasingly important
with the rapidly growing amount of text data available in the World Wide Web.
Among the different strategies proposed to cope with HTC, the Local Classifier
per Node (LCN) approach attains good performance by mirroring the underlying
class hierarchy while enforcing a top-down strategy in the testing step.
However, the problem of embedding hierarchical information (parent-child
relationship) to improve the performance of HTC systems still remains open. A
confidence evaluation method for a selected route in the hierarchy is proposed
to evaluate the reliability of the final candidate labels in an HTC system. In
order to take into account the information embedded in the hierarchy, weight
factors are used to take into account the importance of each level. An
acceptance/rejection strategy in the top-down decision making process is
proposed, which improves the overall categorization accuracy by rejecting a few
percentage of samples, i.e., those with low reliability score. Experimental
results on the Reuters benchmark dataset (RCV1- v2) confirm the effectiveness
of the proposed method, compared to other state-of-the art HTC methods
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