Test Strategies for Embedded ADC Cores in a System-on-Chip, A Case Study

Testing of a deeply embedded mixed-signal core in a System-on-Chip (SoC) is a challenging issue due to the communication bottleneck in accessing the core from external automatic test equipment. Consequently, in many cases the preferred approach is built-in self-test (BIST), where the major part of test activity is performed within the unit-under-test and only final results are communicated to the external tester. IEEE Standard 1500 provides efficient test infrastructure for testing digital cores; however, its applications in mixed-signal core test remain an open issue. In this paper we address the problem of implementing BIST of a mixed-signal core in a IEEE Std 1500 test wrapper and discuss advantages and drawbacks of different test strategies. While the case study is focused on histogram based test of ADC, test strategies of other types of mixed-signal cores related to trade-off between performance (i.e., test time) and required resources are likely to follow similar conclusions

Analog Configurability-Test Scheme for an Embedded Op-Amp Module in TI MSP430 Microcontrollers

This paper proposes the application of the analog configurability test (ACT) approach for an embedded analog configurable circuit, composed by operational amplifiers and interconnection resources that are embedded in the MSP430xG461x microcontrollers family, with the aim of verifying its mode programmability. This test strategy is particularly useful for applications involving in-field circuit reconfiguration, and require reliability and safe operation characteristics. The approach minimizes the cost in hardware overhead by employing only the hardware and software resources of the microcontroller. An embedded test routine sequentially programs selected module configurations, sets the test stimulus, acquires data from the internal ADC, and performs required calculations to determine the gain of the block. The test approach is experimentally evaluated using an embedded-system based real application board. Our experimental results show very good repeatability, with very low errors. These results show that the ACT proposed here is useful for testing the functionality of the EACC under test in a real application context by using a simple strategy at a very low cost.Sociedad Argentina de Informática e Investigación Operativ

Analog Configurability-Test Scheme for an Embedded Op-Amp Module in TI MSP430 Microcontrollers

This paper proposes the application of the analog configurability test (ACT) approach for an embedded analog configurable circuit, composed by operational amplifiers and interconnection resources that are embedded in the MSP430xG461x microcontrollers family, with the aim of verifying its mode programmability. This test strategy is particularly useful for applications involving in-field circuit reconfiguration, and require reliability and safe operation characteristics. The approach minimizes the cost in hardware overhead by employing only the hardware and software resources of the microcontroller. An embedded test routine sequentially programs selected module configurations, sets the test stimulus, acquires data from the internal ADC, and performs required calculations to determine the gain of the block. The test approach is experimentally evaluated using an embedded-system based real application board. Our experimental results show very good repeatability, with very low errors. These results show that the ACT proposed here is useful for testing the functionality of the EACC under test in a real application context by using a simple strategy at a very low cost.Sociedad Argentina de Informática e Investigación Operativ

FPGAs in Industrial Control Applications

The aim of this paper is to review the state-of-the-art of Field Programmable Gate Array (FPGA) technologies and their contribution to industrial control applications. Authors start by addressing various research fields which can exploit the advantages of FPGAs. The features of these devices are then presented, followed by their corresponding design tools. To illustrate the benefits of using FPGAs in the case of complex control applications, a sensorless motor controller has been treated. This controller is based on the Extended Kalman Filter. Its development has been made according to a dedicated design methodology, which is also discussed. The use of FPGAs to implement artificial intelligence-based industrial controllers is then briefly reviewed. The final section presents two short case studies of Neural Network control systems designs targeting FPGAs

Architecture and Advanced Electronics Pathways Toward Highly Adaptive Energy- Efficient Computing

With the explosion of the number of compute nodes, the bottleneck of future computing systems lies in the network architecture connecting the nodes. Addressing the bottleneck requires replacing current backplane-based network topologies. We propose to revolutionize computing electronics by realizing embedded optical waveguides for onboard networking and wireless chip-to-chip links at 200-GHz carrier frequency connecting neighboring boards in a rack. The control of novel rate-adaptive optical and mm-wave transceivers needs tight interlinking with the system software for runtime resource management

PULP-HD: Accelerating Brain-Inspired High-Dimensional Computing on a Parallel Ultra-Low Power Platform

Computing with high-dimensional (HD) vectors, also referred to as $\textit{hypervectors}$, is a brain-inspired alternative to computing with scalars. Key properties of HD computing include a well-defined set of arithmetic operations on hypervectors, generality, scalability, robustness, fast learning, and ubiquitous parallel operations. HD computing is about manipulating and comparing large patterns-binary hypervectors with 10,000 dimensions-making its efficient realization on minimalistic ultra-low-power platforms challenging. This paper describes HD computing's acceleration and its optimization of memory accesses and operations on a silicon prototype of the PULPv3 4-core platform (1.5mm$^2$, 2mW), surpassing the state-of-the-art classification accuracy (on average 92.4%) with simultaneous 3.7$\times$ end-to-end speed-up and 2$\times$ energy saving compared to its single-core execution. We further explore the scalability of our accelerator by increasing the number of inputs and classification window on a new generation of the PULP architecture featuring bit-manipulation instruction extensions and larger number of 8 cores. These together enable a near ideal speed-up of 18.4$\times$ compared to the single-core PULPv3

An embedded sensor node microcontroller with crypto-processors

Wireless sensor network applications range from industrial automation and control, agricultural and environmental protection, to surveillance and medicine. In most applications, data are highly sensitive and must be protected from any type of attack and abuse. Security challenges in wireless sensor networks are mainly defined by the power and computing resources of sensor devices, memory size, quality of radio channels and susceptibility to physical capture. In this article, an embedded sensor node microcontroller designed to support sensor network applications with severe security demands is presented. It features a low power 16-bitprocessor core supported by a number of hardware accelerators designed to perform complex operations required by advanced crypto algorithms. The microcontroller integrates an embedded Flash and an 8-channel 12-bit analog-to-digital converter making it a good solution for low-power sensor nodes. The article discusses the most important security topics in wireless sensor networks and presents the architecture of the proposed hardware solution. Furthermore, it gives details on the chip implementation, verification and hardware evaluation. Finally, the chip power dissipation and performance figures are estimated and analyzed

INCOBAT

Electro-mobility is considered as a key technology to achieve green mobility and fulfil tomorrow’s emission standards. However, different challenges still need to be faced to achieve comparable performances to conventional vehicles and finally obtain market acceptance. Two of these challenges are vehicle range and production costs. In that context, the aim of INCOBAT (October 2013 – December 2016) was to provide innovative and cost efficient battery management systems for next generation HV-batteries. INCOBAT proposes a platform concept that achieves cost reduction, reduced complexity, increased reliability and flexibility while at the same time reaching higher energy efficiency.• Very tight control of the cell function leading to a significant increase of the driving range of the FEV;• Radical cost reduction of the battery management system with respect to current solutions;• Development of modular concepts for system architecture and partitioning, safety, security, reliability as well as verification and validation, thus enabling efficient integration into different vehicle platforms. The INCOBAT project focused on the following twelve technical innovations grouped into four innovation groups, which are summarized in this book:• Customer needs and integration aspects• Transversal innovation• Technology innovation• Transversal innovatio

Techniques of Energy-Efficient VLSI Chip Design for High-Performance Computing

How to implement quality computing with the limited power budget is the key factor to move very large scale integration (VLSI) chip design forward. This work introduces various techniques of low power VLSI design used for state of art computing. From the viewpoint of power supply, conventional in-chip voltage regulators based on analog blocks bring the large overhead of both power and area to computational chips. Motivated by this, a digital based switchable pin method to dynamically regulate power at low circuit cost has been proposed to make computing to be executed with a stable voltage supply. For one of the widely used and time consuming arithmetic units, multiplier, its operation in logarithmic domain shows an advantageous performance compared to that in binary domain considering computation latency, power and area. However, the introduced conversion error reduces the reliability of the following computation (e.g. multiplication and division.). In this work, a fast calibration method suppressing the conversion error and its VLSI implementation are proposed. The proposed logarithmic converter can be supplied by dc power to achieve fast conversion and clocked power to reduce the power dissipated during conversion. Going out of traditional computation methods and widely used static logic, neuron-like cell is also studied in this work. Using multiple input floating gate (MIFG) metal-oxide semiconductor field-effect transistor (MOSFET) based logic, a 32-bit, 16-operation arithmetic logic unit (ALU) with zipped decoding and a feedback loop is designed. The proposed ALU can reduce the switching power and has a strong driven-in capability due to coupling capacitors compared to static logic based ALU. Besides, recent neural computations bring serious challenges to digital VLSI implementation due to overload matrix multiplications and non-linear functions. An analog VLSI design which is compatible to external digital environment is proposed for the network of long short-term memory (LSTM). The entire analog based network computes much faster and has higher energy efficiency than the digital one