Run-time transmission power reconfiguration and adaptive packet relocation in wireless network-on-chip

Network-on-chip (NoC) is an on-chip communication network that allows parallel communication between all cores to improve inter-core performance. Wireless NoC (WiNoC) introduces long-range and high bandwidth radio frequency (RF) interconnects that can possibly reduce the multi-hop communication of the planar metal interconnects in conventional NoC platforms. In WiNoC, RF transceivers account for a significant power consumption, particularly its transmitter, out of its total communication energy. CurrentWiNoC architectures employ constant maximum transmitting power for communicating radio hubs regardless of physical location of the receiver radio hubs. Besides, high transmission power consumption in WiNoC with constant maximum power suffers from significant energy and load imbalance among RF transceivers which lead to hotspot formation, thus affecting the reliability of the onchip network system. There are two main objectives covered by this thesis. Firstly, this work proposes a reconfigurable transmitting power control scheme that, by using bit error rate (BER) estimation obtained at the receiver’s side, dynamically calibrates the transmitting power level needed for communication between the source and destination radio hubs. The proposed scheme achieves significant total system energy reduction by about 40% with an average performance degradation of 3% and with no impact on throughput. The proposed design utilizes a small fraction of both area and power overheads (about 0.1%) out of total transceiver properties. The proposed technique is generic and can be applied to any WiNoC architecture for improving its energy efficiency with a negligible overhead in terms of silicon area. Secondly, an energyaware adaptive packet relocator scheme has been proposed. Based on transmission energy consumption and predefined energy threshold, packets are routed to adjacent transmitter for communication with receiver radio hub, with an aim to balance energy distribution in WiNoC. The proposed strategy alone achieves total communication energy savings of about 8%. A joint scheme of the reconfigurable transmitting power management and energy-aware adaptive packet relocator is also introduced. The scheme consistently results in an energy savings of 30% with minimal performance degradation

A Scalable and Adaptive Network on Chip for Many-Core Architectures

In this work, a scalable network on chip (NoC) for future many-core architectures is proposed and investigated. It supports different QoS mechanisms to ensure predictable communication. Self-optimization is introduced to adapt the energy footprint and the performance of the network to the communication requirements. A fault tolerance concept allows to deal with permanent errors. Moreover, a template-based automated evaluation and design methodology and a synthesis flow for NoCs is introduced

Vorhersagbares und zur Laufzeit adaptierbares On-Chip Netzwerk für gemischt kritische Echtzeitsysteme

The industry of safety-critical and dependable embedded systems calls for even cheaper, high performance platforms that allow flexibility and an efficient verification of safety and real-time requirements. To cope with the increasing complexity of interconnected functions and to reduce the cost and power consumption of the system, multicore systems are used to efficiently integrate different processing units in the same chip. Networks-on-chip (NoCs), as a modular interconnect, are used as a promising solution for such multiprocessor systems on chip (MPSoCs), due to their scalability and performance. For safety-critical systems, a major goal is the avoidance of hazards. For this, safety-critical systems are qualified or even certified to prove the correctness of the functioning under all possible cases. A predictable behaviour of the NoC can help to ease the qualification process of the system. To achieve the required predictability, designers have two classes of solutions: quality of service mechanisms and (formal) analysis. For mixed-criticality systems, isolation and analysis approaches must be combined to efficiently achieve the desired predictability. Traditional NoC analysis and architecture concepts tackle only a subpart of the challenges: they focus on either performance or predictability. Existing, predictable NoCs are deemed too expensive and inflexible to host a variety of applications with opposing constraints. And state-of-the-art analyses neglect certain platform properties to verify the behaviour. Together this leads to a high over-provisioning of the hardware resources as well as adverse impacts on system performance, and on the flexibility of the system. In this work we tackle these challenges and develop a predictable and runtime-adaptable NoC architecture that efficiently integrates mixed-critical applications with opposing constraints. Additionally, we present a modelling and analysis framework for NoCs that accounts for backpressure. This framework enables to evaluate the performance and reliability early at design time. Hence, the designer can assess multiple design decisions by using abstract models and formal approaches.Die Industrie der sicherheitskritischen und zuverlässigen eingebetteten Systeme verlangt nach noch günstigeren, leistungsfähigeren Plattformen, welche Flexibilität und eine effiziente Überprüfung der Sicherheits- und Echtzeitanforderungen ermöglichen. Um der zunehmenden Komplexität der zunehmend vernetzten Funktionen gerecht zu werden und die Kosten und den Stromverbrauch eines Systems zu reduzieren, werden Mehrkern-Systeme eingesetzt. On-Chip Netzwerke werden aufgrund ihrer Skalierbarkeit und Leistung als vielversprechende Lösung für solch Mehrkern-Systeme eingesetzt. Bei sicherheitskritischen Systemen ist die Vermeidung von Gefahren ein wesentliches Ziel. Dazu werden sicherheitskritische Systeme qualifiziert oder zertifiziert, um die Funktionsfähigkeit in allen möglichen Fällen nachzuweisen. Ein vorhersehbares Verhalten des on-Chip Netzwerks kann dabei helfen, den Qualifizierungsprozess des Systems zu erleichtern. Um die erforderliche Vorhersagbarkeit zu erreichen, gibt es zwei Klassen von Lösungen: Quality of Service Mechanismen und (formale) Analyse. Für Systeme mit gemischter Relevanz müssen Isolationsmechanismen und Analyseansätze kombiniert werden, um die gewünschte Vorhersagbarkeit effizient zu erreichen. Traditionelle Analyse- und Architekturkonzepte für on-Chip Netzwerke lösen nur einen Teil dieser Herausforderungen: sie konzentrieren sich entweder auf Leistung oder Vorhersagbarkeit. Existierende vorhersagbare on-Chip Netzwerke werden als zu teuer und unflexibel erachtet, um eine Vielzahl von Anwendungen mit gegensätzlichen Anforderungen zu integrieren. Und state-of-the-art Analysen vernachlässigen bzw. vereinfachen bestimmte Plattformeigenschaften, um das Verhalten überprüfen zu können. Dies führt zu einer hohen Überbereitstellung der Hardware-Ressourcen als auch zu negativen Auswirkungen auf die Systemleistung und auf die Flexibilität des Systems. In dieser Arbeit gehen wir auf diese Herausforderungen ein und entwickeln eine vorhersehbare und zur Laufzeit anpassbare Architektur für on-Chip Netzwerke, welche gemischt-kritische Anwendungen effizient integriert. Zusätzlich stellen wir ein Modellierungs- und Analyseframework für on-Chip Netzwerke vor, das den Paketrückstau berücksichtigt. Dieses Framework ermöglicht es, Designentscheidungen anhand abstrakter Modelle und formaler Ansätze frühzeitig beurteilen

Improving Packet Predictability of Scalable Network-on-Chip Designs without Priority Pre-emptive Arbitration

The quest for improving processing power and efficiency is spawning research into many-core systems with hundreds or thousands of cores. With communication being forecast as the foremost performance bottleneck, Network-on-Chips are the favoured communication infrastructure in the context mainly due to reasons like scalability and power efficiency. However, contention between non-preemptive NoC packets can result in variation in packet latencies thus potentially limiting the overall utilisation of the many-core system. Typical latency predictability enhancement techniques like Virtual Channels or Time Division Multiplexing are usually hardware expensive or non-scalable or both. This research explores the use of dynamic and scalable techniques in Network-on-Chip routers to improve packet predictability by countering Head-of-line blocking (blocked low priority packet blocking a high priority packet) and tailbacking (low priority packet utilising the link that is required by a high priority packet) of non-preemptive packets. The Priority forwarding and tunnelling technique introduced is designed to detect Head-of-line blocking situations so that its internal arbitration parameters can be altered (by forwarding packet parameters down the line) to resolve such issues. The Selective packet splitting technique presented allows resolution of tailbacking by emulating the effect of preemption of packets (by splitting packets) by using a low overhead alternative that manipulates packets. Finally, the thesis presents an architecture that allows the routers to have a notion of timeliness in data packets thus enabling packet arbitration based on application-supplied priority and timeliness thus improving the quality of service given to lower priority packets. Furthermore, the techniques presented in the thesis do not require additional hardware with the increase in size of the NoC. This enables the techniques to be scalable, as the size of the NoC or the number of packet priorities the NoC has to handle does not affect the functionality and operation of the techniques

Design of complex integrated systems based on networks-on-chip: Trading off performance, power and reliability

The steady advancement of microelectronics is associated with an escalating number of challenges for design engineers due to both the tiny dimensions and the enormous complexity of integrated systems. Against this background, this work deals with Network-On-Chip (NOC) as the emerging design paradigm to cope with diverse issues of nanotechnology. The detailed investigations within the chapters focus on the communication-centric aspects of multi-core-systems, whereas performance, power consumption as well as reliability are considered likewise as the essential design criteria

Hardware-accelerated Evolutionary Hard Real-Time Task Mapping for Wormhole Network-on-Chip with Priority-Preemptive Arbitration

Network-on-Chip (NoC) is an alternative on-chip interconnection paradigm to replace existing ones such as Point-to-Point and shared bus. NoCs designed for hard real-time systems need to guarantee the system timing performance, even in the worst-case scenario. A carefully planned task mapping which indicates how tasks are distributed on a NoC platform can improve or guarantee their timing performance. While existing offline mapping optimisations can satisfy timing requirements, this is obtained by sacrificing the flexibility of the system. In addition, the design exploration process will be prolonged with the continuous enlargement of the design space. Online mapping optimisations, by contrast, are affected by low success rates for remapping or a lack of guarantee of systems timing performance after remapping, especially in hard real-time systems. The existing limitations therefore motivate this research to concentrate on the mapping optimisation of real-time NoCs, and specifically dynamic task allocation in hard real-time systems. Four techniques and implementations are proposed to address this issue. The first enhances the evaluation efficiency of a hard real-time evaluation method from a theoretical point of view. The second technique addresses the evaluation efficiency from a practical point of view to enable online hard real-time timing analysis. The third technique advocates a dynamic mapper to enhance the remapping success rate with the accelerated model and architecture. The final technique yields a dynamic mapping algorithm that can search schedulable task allocation for hard real-time NoCs at run time, while simultaneously reducing the task migration cost after remapping

Approches d'optimisation et de personnalisation des réseaux sur puce (NoC : Networks on Chip)

Systems-on-chip (SoC) have become more and more complex due to the development of integrated circuit technology.Recent studies have shown that in order to improve the performance of a specific SoC application domain, the on-chipinter-connects (OCI) architecture must be customized at design-time or at run-time. Related approaches generallyprovide application-specific SoCs tailored to specific applications. The aim of this thesis is to carry out new approachesfor Network-on-Chip (NoC) and study their performances, especially in terms of latency, throughput, energyconsumption and simplicity of implementation.We have proposed an approach to allow designers to customize a candidate OCI architecture by adding strategiclinks in order to match large application workload. The analytical evaluation focuses on improving the physicalparameters of the NoC topology regardless of the application that should run on. The evaluation by simulationfocuses to evaluate the communication performances of the NoC. Simulations results show the effectiveness ofthis approach to improve the NoC performances. We have also introduced a compartmental Fluid-flow basedmodeling approach to allocate required resource for each buffer based on the application traffic pattern. Simulationsare conducted and results show the efficiency of this modeling method for a buffer space optimized allocation.Finally, we proposed a joint approach based on a system dynamics theory for evaluating the performance of a flowcontrol algorithm in NoCs. This algorithm allows NoC elements to dynamically adjust their inflow by using afeedback control-based mechanism. Analytical and simulation results showed the viability of this mechanism forcongestion avoidance in NoCs.Les systèmes embarqués sur puce (SoC : Systems-on-Chip) sont devenus de plus en plus complexes grâce à l’évolution de la technologie des circuits intégrés. Des études récentes ont montré que pour améliorer les performances du réseau su puce (NoC : Network-on-Chip), l’architecture de celui-ci pouvait être personnalisée, soit au moment de la conception, soit au moment de l’exécution. L’objectif principal de cette thèse est d’implémenter de nouvelles approches pour améliorer les performances des NoCs, notamment la latence, le débit, la consommation d’énergie, et la simplicité de mise en œuvre.Nous avons proposé une approche pour permettre aux concepteurs de personnaliser l'architecture d’un NoC par insertion de liens stratégiques, pour qu’elle soit adaptée à de nombreuses applications, sous la contrainte d’un budget limité en termes de nombre de liens. L’évaluation analytique porte sur l’amélioration des paramètres physiques de la topologie du NoC sans tenir compte de l’application qui devrait s’exécuter dessus. L’évaluation par simulation porte sur l’évaluation des performances de communication du NoC. Les résultats de simulations montrent l’efficacité de notre approche pour améliorer les performances du NoC. Nous avons également introduit une approche de modélisation par réseau à compartiments pour allouer les ressources nécessaires pour chaque tampon selon le modèle de trafic de l'application cible. Les résultats de simulations montrent l'efficacité de cette approche de modélisation pour l’allocation optimisée de l'espace tampon. Enfin, nous avons proposé une approche conjointe basée sur la théorie des systèmes dynamiques pour évaluer la performance d'un algorithme de contrôle de flux dans les NoCs. Cet algorithme permet aux éléments du NoC d’ajuster dynamiquement leur entrée en utilisant un mécanisme basé sur le contrôle de flux par rétroaction. Les résultats d’évaluations analytiques et de simulation montrent la viabilité de ce mécanisme pour éviter la congestion dans les NoCs

Book of abstracts of the 10th International Chemical and Biological Engineering Conference: CHEMPOR 2008

This book contains the extended abstracts presented at the 10th International Chemical and Biological Engineering Conference - CHEMPOR 2008, held in Braga, Portugal, over 3 days, from the 4th to the 6th of September, 2008. Previous editions took place in Lisboa (1975, 1889, 1998), Braga (1978), Póvoa de Varzim (1981), Coimbra (1985, 2005), Porto (1993), and Aveiro (2001). The conference was jointly organized by the University of Minho, “Ordem dos Engenheiros”, and the IBB - Institute for Biotechnology and Bioengineering with the usual support of the “Sociedade Portuguesa de Química” and, by the first time, of the “Sociedade Portuguesa de Biotecnologia”. Thirty years elapsed since CHEMPOR was held at the University of Minho, organized by T.R. Bott, D. Allen, A. Bridgwater, J.J.B. Romero, L.J.S. Soares and J.D.R.S. Pinheiro. We are fortunate to have Profs. Bott, Soares and Pinheiro in the Honor Committee of this 10th edition, under the high Patronage of his Excellency the President of the Portuguese Republic, Prof. Aníbal Cavaco Silva. The opening ceremony will confer Prof. Bott with a “Long Term Achievement” award acknowledging the important contribution Prof. Bott brought along more than 30 years to the development of the Chemical Engineering science, to the launch of CHEMPOR series and specially to the University of Minho. Prof. Bott’s inaugural lecture will address the importance of effective energy management in processing operations, particularly in the effectiveness of heat recovery and the associated reduction in greenhouse gas emission from combustion processes. The CHEMPOR series traditionally brings together both young and established researchers and end users to discuss recent developments in different areas of Chemical Engineering. The scope of this edition is broadening out by including the Biological Engineering research. One of the major core areas of the conference program is life quality, due to the importance that Chemical and Biological Engineering plays in this area. “Integration of Life Sciences & Engineering” and “Sustainable Process-Product Development through Green Chemistry” are two of the leading themes with papers addressing such important issues. This is complemented with additional leading themes including “Advancing the Chemical and Biological Engineering Fundamentals”, “Multi-Scale and/or Multi-Disciplinary Approach to Process-Product Innovation”, “Systematic Methods and Tools for Managing the Complexity”, and “Educating Chemical and Biological Engineers for Coming Challenges” which define the extended abstracts arrangements along this book. A total of 516 extended abstracts are included in the book, consisting of 7 invited lecturers, 15 keynote, 105 short oral presentations given in 5 parallel sessions, along with 6 slots for viewing 389 poster presentations. Full papers are jointly included in the companion Proceedings in CD-ROM. All papers have been reviewed and we are grateful to the members of scientific and organizing committees for their evaluations. It was an intensive task since 610 submitted abstracts from 45 countries were received. It has been an honor for us to contribute to setting up CHEMPOR 2008 during almost two years. We wish to thank the authors who have contributed to yield a high scientific standard to the program. We are thankful to the sponsors who have contributed decisively to this event. We also extend our gratefulness to all those who, through their dedicated efforts, have assisted us in this task. On behalf of the Scientific and Organizing Committees we wish you that together with an interesting reading, the scientific program and the social moments organized will be memorable for all.Fundação para a Ciência e a Tecnologia (FCT

Proceedings of the 10th International Chemical and Biological Engineering Conference - CHEMPOR 2008

This volume contains full papers presented at the 10th International Chemical and Biological Engineering Conference - CHEMPOR 2008, held in Braga, Portugal, between September 4th and 6th, 2008.FC