비디오 클럭 주파수 보상 구조를 이용한 디스플레이포트 수신단 설계

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 8. 정덕균.This thesis presents the design of DisplayPort receiver which is a high speed digital display interface replacing existing interfaces such as DVI, HDMI, LVDS and so on. The two prototype chips are fabricated, one is a 5.4/2.7/1.62-Gb/s multi-rate DisplayPort receiver and the other is a 2.7/1.62-Gb/s multi-rate Embedded DisplayPort (eDP) receiver for an intra-panel display interface. The first receiver which is designed to support the external box-to-box display connection provides up to 4K resolution (4096×2160) with the maximum data rate of 21.6 Gb/s when 4 lanes are all used. The second one aims to connect internal chip-to-chip connection such as graphic processors to display panels in notebooks or tablet PCs. It supports the maximum data rate of 10.8 Gb/s with 4-lane operation which is able to provide the resolution of WQXGA (2560×1600). Since there is no dedicated clock channel, it must contain clock and data recovery (CDR) circuit to extract the link clock from the data stream. All-Digital CDR (ADCDR) is adopted for area efficiency and better performances of the multi-rate operation. The link rate is fixed but the video clock frequency range is fairly wide for supporting all display resolutions and frame rates. Thus, the wide range video clock frequency synthesizer is essential for reconstructing the transmitted video data. A source device starts link training before transmitting video data to recover the clock and establish the link. When the loss of synchronization between the source device and the sink device happens, it usually restarts the link training and try to re-establish the link. Since link training spends several milliseconds for initializing, the video image is not displayed properly in the sink device during this interval. The proposed clock recovery scheme can significantly shorten the time to recover from the link failure with the ADCDR topology. Once the link is established after link training, the ADCDR memorizes the DCO codes of the synchronization state and when the loss of synchronization happens, it restores the previous DCO code so that the clock is quickly recovered from the failure state without the link re-training. The direct all-digital frequency synthesizer is proposed to generate the cycle-accurate video clock frequency. The video clock frequency has wide range to cover all display formats and is determined by the division ratio of large M and N values. The proposed frequency synthesizer using a programmable integer divider and a multi-phase switching fractional divider with the delta-sigma modulation exhibits better performances and reduces the design complexity operating with the existing clock from the ADCDR circuit. In asynchronous clock system, the transmitted M value which changes over time is measured by using a counter running with the long reference period (N cycles) and updated once per blank period. Thus, the transmitted M is not accurate due to its low update rate, transport latency and quantization error. The proposed frequency error compensation scheme resolves these problems by monitoring the status of FIFO between the clock domains. The first prototype chip is fabricated in a 65-nm CMOS process and the physical layer occupies 1.39 mm2 and the estimated area of the link layer is 2.26 mm2. The physical layer dissipates 86/101/116 mW at 1.62/2.7/5.4 Gb/s data rate with all 4-lane operation. The power consumption of the link layer is 107/145/167 mW at 1.62/2.7/5.4 Gb/s. The second prototype chip, fabricated in a 0.13μm CMOS process, presents the physical layer area of 1.59 mm2 and the link layer area of 3.01 mm2. The physical layer dissipates 21 mW at 1.62 Gb/s and 29 mW at 2.7 Gb/s with 2-lane operation. The power consumption of the link layer is 31 mW at 1.62 Gb/s and 41 mW at 2.7 Gb/s with 2-lane operation. The core area of the video clock synthesizer occupies 0.04 mm2 and the power dissipation is 5.5 mW at a low bit rate and 9.1 mW at a high bit rate. The output frequency range is 25 to 330 MHz.ABSTRACT I CONTENTS IV LIST OF FIGURES VII LIST OF TABLES XII CHAPTER 1 INTRODUCTION 1 1.1 BACKGROUND 1 1.2 MOTIVATION 4 1.3 THESIS ORGANIZATION 12 CHAPTER 2 DIGITAL DISPLAY INTERFACE 13 2.1 OVERVIEW 13 2.2 DISPLAYPORT INTERFACE CHARACTERISTICS 18 2.2.1 DISPLAYPORT VERSION 1.2 18 2.2.2 EMBEDDED DISPLAYPORT VERSION 1.2 21 2.3 DISPLAYPORT INTERFACE ARCHITECTURE 23 2.3.1 LAYERED ARCHITECTURE 23 2.3.2 MAIN STREAM PROTOCOL 27 2.3.3 INITIALIZATION AND LINK TRAINING 30 2.3.3 VIDEO STREAM CLOCK RECOVERY 35 CHAPTER 3 DESIGN OF DISPLAYPORT RECEIVER 39 3.1 OVERVIEW 39 3.2 PHYSICAL LAYER 43 3.3 LINK LAYER 55 3.3.1 OVERALL ARCHITECTURE 55 3.3.2 AUX CHANNEL 58 3.3.3 VIDEO TIMING GENERATION 61 3.3.4 CONTENT PROTECTION 63 3.3.5 AUDIO TRANSMISSION 66 3.4 EXPERIMENTAL RESULTS 68 CHAPTER 4 DESIGN OF EMBEDDED DISPLAYPORT RECEIVER 81 4.1 OVERVIEW 81 4.2 PHYSICAL LAYER 84 4.3 LINK LAYER 88 4.3.1 OVERALL ARCHITECTURE 88 4.3.2 MAIN LINK STREAM 90 4.3.3 CONTENT PROTECTION 93 4.4 PROPOSED CLOCK RECOVERY SCHEME 94 4.5 EXPERIMENTAL RESULTS 100 CHAPTER 5 PROPOSED VIDEO CLOCK SYNTHESIZER AND FREQUENCY CONTROL SCHEME 113 5.1 MOTIVATION 113 5.2 PROPOSED VIDEO CLOCK SYNTHESIZER 115 5.3 BUILDING BLOCKS 121 5.4 FREQUENCY ERROR COMPENSATION 126 5.5 EXPERIMENTAL RESULTS 131 CHAPTER 6 CONCLUSION 138 BIBLIOGRAPHY 141 초 록 152Docto

Stochastic dynamics and wavelets techniques for system response analysis and diagnostics: Diverse applications in structural and biomedical engineering

In the first part of the dissertation, a novel stochastic averaging technique based on a Hilbert transform definition of the oscillator response displacement amplitude is developed. In comparison to standard stochastic averaging, the requirement of “a priori” determination of an equivalent natural frequency is bypassed, yielding flexibility in the ensuing analysis and potentially higher accuracy. Further, the herein proposed Hilbert transform based stochastic averaging is adapted for determining the time-dependent survival probability and first-passage time probability density function of stochastically excited nonlinear oscillators, even endowed with fractional derivative terms. To this aim, a Galerkin scheme is utilized to solve approximately the backward Kolmogorov partial differential equation governing the survival probability of the oscillator response. Next, the potential of the stochastic averaging technique to be used in conjunction with performance-based engineering design applications is demonstrated by proposing a stochastic version of the widely used incremental dynamic analysis (IDA). Specifically, modeling the excitation as a non-stationary stochastic process possessing an evolutionary power spectrum (EPS), an approximate closed-form expression is derived for the parameterized oscillator response amplitude probability density function (PDF). In this regard, IDA surfaces are determined providing the conditional PDF of the engineering demand parameter (EDP) for a given intensity measure (IM) value. In contrast to the computationally expensive Monte Carlo simulation, the methodology developed herein determines the IDA surfaces at minimal computational cost. In the second part of the dissertation, a novel multiple-input/single-output (MISO) system identification technique is developed for parameter identification of nonlinear and time-variant oscillators with fractional derivative terms subject to incomplete non-stationary data. The technique utilizes a representation of the nonlinear restoring forces as a set of parallel linear sub-systems. Next, a recently developed L1-norm minimization procedure based on compressive sensing theory is applied for determining the wavelet coefficients of the available incomplete non-stationary input-output (excitation-response) data. Several numerical examples are considered for assessing the reliability of the technique, even in the presence of incomplete and corrupted data. These include a 2-DOF time-variant Duffing oscillator endowed with fractional derivative terms, as well as a 2-DOF system subject to flow-induced forces where the non-stationary sea state possesses a recently proposed evolutionary version of the JONSWAP spectrum. In the third part of this dissertation, a joint time-frequency analysis technique based on generalized harmonic wavelets (GHWs) is developed for dynamic cerebral autoregulation (DCA) performance quantification. DCA is the continuous counter-regulation of the cerebral blood flow by the active response of cerebral blood vessels to the spontaneous or induced blood pressure fluctuations. Specifically, various metrics of the phase shift and magnitude of appropriately defined GHW-based transfer functions are determined based on data points over the joint time-frequency domain. The potential of these metrics to be used as a diagnostics tool for indicating healthy versus impaired DCA function is assessed by considering both healthy individuals and patients with unilateral carotid artery stenosis. Next, another application in biomedical engineering is pursued related to the Pulse Wave Imaging (PWI) technique. This relies on ultrasonic signals for capturing the propagation of pressure pulses along the carotid artery, and eventually for prognosis of focal vascular diseases (e.g., atherosclerosis and abdominal aortic aneurysm). However, to obtain a high spatio-temporal resolution the data are acquired at a high rate, in the order of kilohertz, yielding large datasets. To address this challenge, an efficient data compression technique is developed based on the multiresolution wavelet decomposition scheme, which exploits the high correlation of adjacent RF-frames generated by the PWI technique. Further, a sparse matrix decomposition is proposed as an efficient way to identify the boundaries of the arterial wall in the PWI technique

Analog Implementation of Fractional-Order Elements and Their Applications

With advancements in the theory of fractional calculus and also with widespread engineering application of fractional-order systems, analog implementation of fractional-order integrators and differentiators have received considerable attention. This is due to the fact that this powerful mathematical tool allows us to describe and model a real-world phenomenon more accurately than via classical “integer” methods. Moreover, their additional degree of freedom allows researchers to design accurate and more robust systems that would be impractical or impossible to implement with conventional capacitors. Throughout this thesis, a wide range of problems associated with analog circuit design of fractional-order systems are covered: passive component optimization of resistive-capacitive and resistive-inductive type fractional-order elements, realization of active fractional-order capacitors (FOCs), analog implementation of fractional-order integrators, robust fractional-order proportional-integral control design, investigation of different materials for FOC fabrication having ultra-wide frequency band, low phase error, possible low- and high-frequency realization of fractional-order oscillators in analog domain, mathematical and experimental study of solid-state FOCs in series-, parallel- and interconnected circuit networks. Consequently, the proposed approaches in this thesis are important considerations in beyond the future studies of fractional dynamic systems

Demonstration of Inexact Computing Implemented in the JPEG Compression Algorithm using Probabilistic Boolean Logic applied to CMOS Components

Probabilistic computing offers potential improvements in energy, performance, and area compared with traditional digital design. This dissertation quantifies energy and energy-delay tradeoffs in digital adders, multipliers, and the JPEG image compression algorithm. This research shows that energy demand can be cut in half with noisesusceptible16-bit Kogge-Stone adders that deviate from the correct value by an average of 3 in 14 nanometer CMOS FinFET technology, while the energy-delay product (EDP) is reduced by 38 . This is achieved by reducing the power supply voltage which drives the noisy transistors. If a 19 average error is allowed, the adders are 13 times more energy-efficient and the EDP is reduced by 35 . This research demonstrates that 92 of the color space transform and discrete cosine transform circuits within the JPEG algorithm can be built from inexact components, and still produce readable images. Given the case in which each binary logic gate has a 1 error probability, the color space transformation has an average pixel error of 5.4 and a 55 energy reduction compared to the error-free circuit, and the discrete cosine transformation has a 55 energy reduction with an average pixel error of 20

Evolution of Thermally Pulsing Asymptotic Giant Branch Stars. IV. Constraining Mass Loss and Lifetimes of Low Mass, Low Metallicity AGB Stars

The evolution and lifetimes of thermally pulsating asymptotic giant branch (TP-AGB) stars suffer from significant uncertainties. In this work, we analyze the numbers and luminosity functions of TP-AGB stars in six quiescent, low metallicity ([Fe/H] 72 -0.86) galaxies taken from the ACS Nearby Galaxy Survey Treasury sample, using Hubble Space Telescope (HST) photometry in both optical and near-infrared filters. The galaxies contain over 1000 TP-AGB stars (at least 60 per field). We compare the observed TP-AGB luminosity functions and relative numbers of TP-AGB and red giant branch (RGB) stars, N TP-AGB/N RGB, to models generated from different suites of TP-AGB evolutionary tracks after adopting star formation histories derived from the HST deep optical observations. We test various mass-loss prescriptions that differ in their treatments of mass loss before the onset of dust-driven winds (pre-dust). These comparisons confirm that pre-dust mass loss is important, since models that neglect pre-dust mass loss fail to explain the observed N TP-AGB/N RGB ratio or the luminosity functions. In contrast, models with more efficient pre-dust mass loss produce results consistent with observations. We find that for [Fe/H] 72 -0.86, lower mass TP-AGB stars (M 72 1 M ) must have lifetimes of 3c0.5 Myr and higher masses (M 72 3 M ) must have lifetimes 72 1.2 Myr. In addition, assuming our best-fitting mass-loss prescription, we show that the third dredge-up has no significant effect on TP-AGB lifetimes in this mass and metallicity range. \ua9 2014. The American Astronomical Society. All rights reserved.

The aperiodic nature of mullite

181 p.Different methods were applied to investigate the vacancy and Al/Si order in mullite. At first the symmetry was analysed thoroughly to derive constraints on the vacancy distribution based on crystal chemical premises. On this basis a superspace model was developed that defines the polyhedra network consisting of octahedra, tetrahedral tricluster units and tetrahedral dicluster units as a function of the modulation wave vector and the vacancy concentration. Refinements of superspace models based on synchrotron single crystal X-ray diffraction measurements indicate that in the real structure the identified pattern is present, but with a decreased degree of order. Different samples exhibit different degrees of order suggesting that mainly disordered and fully ordered mullite crystals exist. The Al/Si ordering could not be derived from symmetry constraints and the occupancy of Si could not be refined. Nevertheless, an Al/Si ordering pattern could be identified from the analysis of the displacive modulation.The dependence of the satellite reflections on the chemical composition was studied with precession electron diffraction tomography and density functional theory. This allowed to characterise the structural modulation on a new level and reveal the fundamental ordering patterns that define the crystal structure of mullite in terms of vacancy, tricluster and Al/Si order. The understanding of the crystal structure forms a new basis for future research on the properties of mullite and related applications

The aperiodic nature of mullite

181 p.Different methods were applied to investigate the vacancy and Al/Si order in mullite. At first the symmetry was analysed thoroughly to derive constraints on the vacancy distribution based on crystal chemical premises. On this basis a superspace model was developed that defines the polyhedra network consisting of octahedra, tetrahedral tricluster units and tetrahedral dicluster units as a function of the modulation wave vector and the vacancy concentration. Refinements of superspace models based on synchrotron single crystal X-ray diffraction measurements indicate that in the real structure the identified pattern is present, but with a decreased degree of order. Different samples exhibit different degrees of order suggesting that mainly disordered and fully ordered mullite crystals exist. The Al/Si ordering could not be derived from symmetry constraints and the occupancy of Si could not be refined. Nevertheless, an Al/Si ordering pattern could be identified from the analysis of the displacive modulation.The dependence of the satellite reflections on the chemical composition was studied with precession electron diffraction tomography and density functional theory. This allowed to characterise the structural modulation on a new level and reveal the fundamental ordering patterns that define the crystal structure of mullite in terms of vacancy, tricluster and Al/Si order. The understanding of the crystal structure forms a new basis for future research on the properties of mullite and related applications