학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 8. 정덕균.This thesis presents the design of DisplayPort receiver which is a high speed digital display interface replacing existing interfaces such as DVI, HDMI, LVDS and so on. The two prototype chips are fabricated, one is a 5.4/2.7/1.62-Gb/s multi-rate DisplayPort receiver and the other is a 2.7/1.62-Gb/s multi-rate Embedded DisplayPort (eDP) receiver for an intra-panel display interface.
The first receiver which is designed to support the external box-to-box display connection provides up to 4K resolution (4096×2160) with the maximum data rate of 21.6 Gb/s when 4 lanes are all used. The second one aims to connect internal chip-to-chip connection such as graphic processors to display panels in notebooks or tablet PCs. It supports the maximum data rate of 10.8 Gb/s with 4-lane operation which is able to provide the resolution of WQXGA (2560×1600). Since there is no dedicated clock channel, it must contain clock and data recovery (CDR) circuit to extract the link clock from the data stream. All-Digital CDR (ADCDR) is adopted for area efficiency and better performances of the multi-rate operation. The link rate is fixed but the video clock frequency range is fairly wide for supporting all display resolutions and frame rates. Thus, the wide range video clock frequency synthesizer is essential for reconstructing the transmitted video data.
A source device starts link training before transmitting video data to recover the clock and establish the link. When the loss of synchronization between the source device and the sink device happens, it usually restarts the link training and try to re-establish the link. Since link training spends several milliseconds for initializing, the video image is not displayed properly in the sink device during this interval. The proposed clock recovery scheme can significantly shorten the time to recover from the link failure with the ADCDR topology. Once the link is established after link training, the ADCDR memorizes the DCO codes of the synchronization state and when the loss of synchronization happens, it restores the previous DCO code so that the clock is quickly recovered from the failure state without the link re-training.
The direct all-digital frequency synthesizer is proposed to generate the cycle-accurate video clock frequency. The video clock frequency has wide range to cover all display formats and is determined by the division ratio of large M and N values. The proposed frequency synthesizer using a programmable integer divider and a multi-phase switching fractional divider with the delta-sigma modulation exhibits better performances and reduces the design complexity operating with the existing clock from the ADCDR circuit. In asynchronous clock system, the transmitted M value which changes over time is measured by using a counter running with the long reference period (N cycles) and updated once per blank period. Thus, the transmitted M is not accurate due to its low update rate, transport latency and quantization error. The proposed frequency error compensation scheme resolves these problems by monitoring the status of FIFO between the clock domains.
The first prototype chip is fabricated in a 65-nm CMOS process and the physical layer occupies 1.39 mm2 and the estimated area of the link layer is 2.26 mm2. The physical layer dissipates 86/101/116 mW at 1.62/2.7/5.4 Gb/s data rate with all 4-lane operation. The power consumption of the link layer is 107/145/167 mW at 1.62/2.7/5.4 Gb/s. The second prototype chip, fabricated in a 0.13μm CMOS process, presents the physical layer area of 1.59 mm2 and the link layer area of 3.01 mm2. The physical layer dissipates 21 mW at 1.62 Gb/s and 29 mW at 2.7 Gb/s with 2-lane operation. The power consumption of the link layer is 31 mW at 1.62 Gb/s and 41 mW at 2.7 Gb/s with 2-lane operation. The core area of the video clock synthesizer occupies 0.04 mm2 and the power dissipation is 5.5 mW at a low bit rate and 9.1 mW at a high bit rate. The output frequency range is 25 to 330 MHz.ABSTRACT I
CONTENTS IV
LIST OF FIGURES VII
LIST OF TABLES XII
CHAPTER 1 INTRODUCTION 1
1.1 BACKGROUND 1
1.2 MOTIVATION 4
1.3 THESIS ORGANIZATION 12
CHAPTER 2 DIGITAL DISPLAY INTERFACE 13
2.1 OVERVIEW 13
2.2 DISPLAYPORT INTERFACE CHARACTERISTICS 18
2.2.1 DISPLAYPORT VERSION 1.2 18
2.2.2 EMBEDDED DISPLAYPORT VERSION 1.2 21
2.3 DISPLAYPORT INTERFACE ARCHITECTURE 23
2.3.1 LAYERED ARCHITECTURE 23
2.3.2 MAIN STREAM PROTOCOL 27
2.3.3 INITIALIZATION AND LINK TRAINING 30
2.3.3 VIDEO STREAM CLOCK RECOVERY 35
CHAPTER 3 DESIGN OF DISPLAYPORT RECEIVER 39
3.1 OVERVIEW 39
3.2 PHYSICAL LAYER 43
3.3 LINK LAYER 55
3.3.1 OVERALL ARCHITECTURE 55
3.3.2 AUX CHANNEL 58
3.3.3 VIDEO TIMING GENERATION 61
3.3.4 CONTENT PROTECTION 63
3.3.5 AUDIO TRANSMISSION 66
3.4 EXPERIMENTAL RESULTS 68
CHAPTER 4 DESIGN OF EMBEDDED DISPLAYPORT RECEIVER 81
4.1 OVERVIEW 81
4.2 PHYSICAL LAYER 84
4.3 LINK LAYER 88
4.3.1 OVERALL ARCHITECTURE 88
4.3.2 MAIN LINK STREAM 90
4.3.3 CONTENT PROTECTION 93
4.4 PROPOSED CLOCK RECOVERY SCHEME 94
4.5 EXPERIMENTAL RESULTS 100
CHAPTER 5 PROPOSED VIDEO CLOCK SYNTHESIZER AND FREQUENCY CONTROL SCHEME 113
5.1 MOTIVATION 113
5.2 PROPOSED VIDEO CLOCK SYNTHESIZER 115
5.3 BUILDING BLOCKS 121
5.4 FREQUENCY ERROR COMPENSATION 126
5.5 EXPERIMENTAL RESULTS 131
CHAPTER 6 CONCLUSION 138
BIBLIOGRAPHY 141
초 록 152Docto
