GaN Power Devices: Discerning Application-Specific Challenges and Limitations in HEMTs

GaN power devices are typically used in the 600 V market, for high efficiency, high power-density systems. For these devices, the lateral optimization of gate-to-drain, gate, and gate-to-source lengths, as well as gate field-plate length are critical for optimizing breakdown voltage and performance. This work presents a systematic study of lateral scaling optimization for high voltage devices to minimize figure of merit and maximize breakdown voltage. In addition, this optimization is extended for low voltage devices ( \u3c 100 V), presenting results to optimize both lateral features and vertical features. For low voltage design, simulation work suggests that breakdown is more reliant on punch-through as the primary breakdown mechanism rather than on vertical leakage current as is the case with high-voltage devices. A fabrication process flow has been developed for fabricating Schottky-gate, and MIS-HEMT structures at UCF in the CREOL cleanroom. The fabricated devices were designed to validate the simulation work for low voltage GaN devices. The UCF fabrication process is done with a four layer mask, and consists of mesa isolation, ohmic recess etch, an optional gate insulator layer, ohmic metallization, and gate metallization. Following this work, the fabrication process was transferred to the National Nano Device Laboratories (NDL) in Hsinchu, Taiwan, to take advantage of the more advanced facilities there. Following fabrication, a study has been performed on defect induced performance degradation, leading to the observation of a new phenomenon: trap induced negative differential conductance (NDC). Typically NDC is caused by self-heating, however by implementing a substrate bias test in conjunction with pulsed I-V testing, the NDC seen in our fabricated devices has been confirmed to be from buffer traps that are a result of poor channel carrier confinement during the dc operating condition

Wide Bandgap Based Devices: Design, Fabrication and Applications, Volume II

Wide bandgap (WBG) semiconductors are becoming a key enabling technology for several strategic fields, including power electronics, illumination, and sensors. This reprint collects the 23 papers covering the full spectrum of the above applications and providing contributions from the on-going research at different levels, from materials to devices and from circuits to systems

Modeling of gallium nitride transistors for high power and high temperature applications

Wide bandgap (WBG) semiconductors such as GaN and SiC are emerging as promising alternatives to Si for new generation of high efficiency power devices. GaN has attracted a lot of attention recently because of its superior material properties leading to potential realization of power transistors for high power, high frequency, and high temperature applications. In order to utilize the full potential of GaN-based power transistors, proper device modeling is essential to verify its operation and improve the design efficiency. In this view, this research work presents modeling and characterization of GaN transistors for high power and high temperature applications. The objective of this research work includes three key areas of GaN device modeling such as physics-based analytical modeling, device simulation with numerical simulator and electrothermal SPICE model for circuit simulation. The analytical model presented in this dissertation enables understanding of the fundamental physics of this newly emerged GaN device technology to improve the operation of existing device structures and to optimize the device configuration in the future. The numerical device simulation allows to verify the analytical model and study the impact of different device parameters. An empirical SPICE model for standard circuit simulator has been developed and presented in the dissertation which allows simulation of power electronic circuits employing GaN power devices. The empirical model provides a good approximation of the device behavior and creates a link between the physics-based analytical model and the actual device testing data. Furthermore, it includes an electrothermal model which can predict the device behavior at elevated temperatures as required for high temperature applications.Includes bibliographical reference

Design, Fabrication and Characterization of GaN HEMTs for Power Switching Applications

The unique properties of the III-nitride heterostructure, consisting of gallium nitride (GaN), aluminium nitride (AlN) and their ternary compounds (e.g. AlGaN, InAlN), allow for the fabrication of high electron mobility transistors (HEMTs). These devices exhibit high breakdown fields, high electron mobilities and small parasitic capacitances, making them suitable for wireless communication and power electronic applications. In this work, GaN-based power switching HEMTs and low voltage, short-channel HEMTs were designed, fabricated, and characterized.In the first part of the thesis, AlGaN/GaN-on-SiC high voltage metal-insulator-semiconductor (MIS)HEMTs fabricated on a novel ‘buffer-free’ heterostructure are presented. This heterostructure effectively suppresses buffer-related trapping effects while maintaining high electron confinement and low leakage currents, making it a viable material for high voltage, power electronic HEMTs. This part of the thesis covers device processing techniques to minimize leakage currents and maximize breakdown voltages in these ‘buffer-free’ MISHEMTs. Additionally, a recess-etched, Ta-based, ohmic contact process was utilized to form low-resistive ohmic contacts with contact resistances of 0.44-0.47 Ω∙mm. High voltage operation can be achieved by employing a temperature-stable nitrogen implantation isolation process, which results in three-terminal breakdown fields of 98-123 V/μm. By contrast, mesa isolation techniques exhibit breakdown fields below 85 V/μm and higher off-state leakage currents. Stoichiometric low-pressure chemical vapor deposition (LPCVD) SiNx passivation layers suppress gate currents through the AlGaN barrier below 10 nA/mm over 1000 V, which is more than two orders of magnitude lower compared to Si-rich SiNx passivation layers. A 10% dynamic on-resistance increase at 240 V was measured in HEMTs with stoichiometric SiNx passivation, which is likely caused by slow traps with time constants over 100 ms. SiNx gate dielectrics display better electrical isolation at high voltages compared to HfO2 and Ta2O5. However, the two gate oxides exhibit threshold voltages (Vth) above -2 V, making them a promising alternative for the fabrication of recess-etched normally-off MISHEMTs.Reducing the gate length (Lg) to minimize losses and increase the operating frequency in GaN HEMTs also entails more severe short-channel effects (SCEs), limiting gain, output power and the maximum off-state voltage. In the second part of the thesis, SCEs were studied in short-channel GaN HEMTs using a drain-current injection technique (DCIT). The proposed method allows Vth to be obtained for a wide range of drain-source voltages (Vds) in one measurement, which then can be used to calculate the drain-induced barrier lowering (DIBL) as a rate-of-change of Vth with respect to Vds. The method was validated using HEMTs with a Fe-doped GaN buffer layer and a C-doped AlGaN back-barrier with thin channel layers. Supporting technology computer-aided design (TCAD) simulations indicate that the large increase in DIBL is caused by buffer leakage. This method could be utilized to optimize buffer design and gate lengths to minimize on-state losses and buffer leakage currents in power switching HEMTs

Wide Bandgap Based Devices

Emerging wide bandgap (WBG) semiconductors hold the potential to advance the global industry in the same way that, more than 50 years ago, the invention of the silicon (Si) chip enabled the modern computer era. SiC- and GaN-based devices are starting to become more commercially available. Smaller, faster, and more efficient than their counterpart Si-based components, these WBG devices also offer greater expected reliability in tougher operating conditions. Furthermore, in this frame, a new class of microelectronic-grade semiconducting materials that have an even larger bandgap than the previously established wide bandgap semiconductors, such as GaN and SiC, have been created, and are thus referred to as “ultra-wide bandgap” materials. These materials, which include AlGaN, AlN, diamond, Ga2O3, and BN, offer theoretically superior properties, including a higher critical breakdown field, higher temperature operation, and potentially higher radiation tolerance. These attributes, in turn, make it possible to use revolutionary new devices for extreme environments, such as high-efficiency power transistors, because of the improved Baliga figure of merit, ultra-high voltage pulsed power switches, high-efficiency UV-LEDs, and electronics. This Special Issue aims to collect high quality research papers, short communications, and review articles that focus on wide bandgap device design, fabrication, and advanced characterization. The Special Issue will also publish selected papers from the 43rd Workshop on Compound Semiconductor Devices and Integrated Circuits, held in France (WOCSDICE 2019), which brings together scientists and engineers working in the area of III–V, and other compound semiconductor devices and integrated circuits

Effects of surface plasma treatment on threshold voltage hysteresis and instability in metal-insulator-semiconductor (MIS) AlGaN/GaN heterostructure HEMTs

In a bid to understand the commonly observed hysteresis in the threshold voltage (VTH) in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors during forward gate bias stress, we have analyzed a series of measurements on devices with no surface treatment and with two different plasma treatments before the in-situ Al2O3 deposition. The observed changes between samples were quasi-equilibrium VTH, forward bias related VTH hysteresis, and electrical response to reverse bias stress. To explain these effects, a disorder induced gap state model, combined with a discrete level donor, at the dielectric/semiconductor interface was employed. Technology Computer-Aided Design modeling demonstrated the possible differences in the interface state distributions that could give a consistent explanation for the observations

The effects of carbon on the bidirectional threshold voltage instabilities induced by negative gate bias stress in GaN MIS-HEMTs

In this paper, numerical device simulations are used to point out the possible contributions of carbon doping to the threshold voltage instabilities induced by negative gate bias stress in AlGaN/GaN metal–insulator–semiconductor high-electron mobility transistors. It is suggested that carbon can have a role in both negative and positive threshold voltage shifts, as a result of (1) the changes in the total negative charge stored in the carbon-related acceptor traps in the GaN buffer, and (2) the attraction of carbon-related free holes to the device surface and their capture into interface traps or recombination with gate-injected electrons. For a proper device optimization of carbon-doped MIS-HEMTs, it is therefore important to take these mechanisms into account, in addition to those related to defects in the gate dielectric volume and interface which are conventionally held responsible for threshold voltage instabilities

Optimization of Ohmic Contacts and Surface Passivation for ‘Buffer-Free’ GaN HEMT Technologies

Gallium nitride high electron mobility transistors (GaN HEMTs) draw attention from high frequency and high power industries due to unique properties including high electron mobility and saturation velocity combined with high breakdown voltage. This makes GaN HEMTs suitable for power devices with high switching speed and high frequency applications with high power density requirements. However, the device performance is still partly limited by problems associated with the formation of low resistivity ohmic contact, trapping effects, and the confinement of the two-dimensional electron gas (2DEG).\ua0\ua0\ua0 In this work, reproducible deeply recessed Ta-based ohmic contacts with a low contact resistance of 0.2 - 0.3 Ωmm, a low annealing temperature of 550 - 600 \ub0C, and a large process window were optimized. Low annealing temperature reduces the risk of 2DEG degradation and promotes better morphology of the ohmic contacts. Deeply recessed ohmic contacts beyond the barrier layers make the process less sensitive to the etching depth since the ohmic contacts are formed on the sidewall of the recess. The concept of deeply recessed low resistivity ohmic contacts is also successfully demonstrated on different epi-structures with different barrier designs.\ua0\ua0\ua0 Passivation with silicon nitride (SiN) is an effective method to suppress electron trapping effects. Low Pressure Chemical Vapor Deposition (LPCVD) of SiN has shown to result in high quality dielectrics with excellent passivation effect. However, the surface traps are not fully removed after passivation due to dangling-bonds and native oxide layer at the interface of passivation and epi-structure. Therefore, a plasma-free in-situ NH3 pretreatment method before the deposition of the SiN passivation was studied. The samples with the pretreatment present a 38% lower surface-related current collapse and a 50% lower dynamic on-resistance than the samples without the pretreatment. The improved dynamic performance and lower dispersion directly yield a 30% higher output power of (3.4 vs. 2.6 W/mm) and a better power added efficiency (44% vs. 39%) at 3 GHz. Furthermore, it was found that a longer pretreatment duration improves the uniformity of device performance.\ua0\ua0\ua0 Traditionally, decreasing leakage currents in the buffer and improving electron confinement to the 2DEG are achieved by intentional acceptor-like dopants (iron and carbon) in the GaN buffer and back-barrier layer made by a ternary III-nitride material. However, electron trapping effects and thermal resistivity increase due to the dopants and the ternary material, respectively. In this thesis, a novel approach, where a unique epitaxial scheme permits a thickness reduction of the unintentional-doped (UID) GaN layer down to 250 nm, as compared to a normal thickness of 2 μm. In this way, the AlN nucleation layer effectively act as a back-barrier. The approached, named QuanFINE is investigated and benchmarked to a conventional epi-structure with a thick Fe-doped-GaN buffer. A 2DEG mobility of 2000 cm^2/V-s and the 2DEG concentration of 1.1∙10^13 cm^-2 on QuanFINE indicate that the 2DEG properties are not sacrificed with a thin UID-GaN layer. Thanks to the thin UID-GaN layer of QuanFINE, trapping effects are reduced. Comparable output power of 4.1 W/mm and a PAE of 40% at 3 GHz of both QuanFINE and conventional Fe-doped thick GaN buffer sample are measured

AlGaN/GaN 전력소자의 특성 향상을 위한 식각과 절연막에 관한 연구

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2020. 8. 서광석.최근 에너지 위기와 환경규제 강화, 친환경 녹색성장 등의 이슈가 대두되어 에너지 절감과 환경 보호 분야에 IT 기술을 접목, 활용하는 그린 IT 패러다임이 부각되고 있다. 현재 고유가 환경규제 강화에 대응하기 위해 하이브리드 자동차, 전기자동차 등 친환경 미래형 자동차 개발이 요구되고 있으며, 자동차에서 전장부품이 차지하는 원가비중은 약 40%까지 달할 것으로 전망되고 이 중 반도체가 차지하는 비용은 약 30% 정도로 추정된다. 이러한 자동차 전장부품에서 전력소자가 핵심부품으로 자리 잡을 전망이다. 지금까지는 실리콘 기반의 전력소자 기술이 전력반도체 시장의 대부분을 주도하고 있지만 전력기기 로드맵에 의하면 전력밀도가 해를 거듭하면서 지속적으로 증가하기 때문에 내열, 내압, 전력손실, 전력밀도 등에서 나타나는 많은 한계를 가지고 있는 현재의 실리콘 기반 전력시스템은 효율이 눈에 띄게 감소할 것이 자명하므로 전력시스템의 전력전송효율과 신뢰성의 중요성이 크게 대두되고 있다. 이 같은 사회적 요구로 볼 때 현재의 실리콘 전력소자의 기술적 한계를 뛰어넘는 고효율의 차세대 전력반도체 소자의 개발이 시급히 요구되며 SiC와 GaN와 같은 광대역 반도체가 차세대 전력반도체 소재로 유력해지고 있다. 또한 전력시스템에서는 시스템의 안전성과 회로의 간략화를 위하여 normally-off (증강형) 전력소자가 요구되기 때문에 normally-off (증강형) GaN 전력소자에 대한 개발이 필수적이다. 본 그룹에서는 gate-recess 공정을 이용하여 normally-off 동작을 실현하는 연구를 진행하였고, gate-recess 시 발생하는 식각 데미지를 줄이고 우수한 성능의 게이트 절연막을 개발하여 GaN 전력 반도체 소자의 전기적 특성 및 신뢰성을 개선하는 연구를 진행하였다. 식각 연구에서는 최종적으로 셀프 DC 바이어스가 낮은 O2, BCl3 플라즈마를 이용한 atomic layer etching을 개발하였고, 이를 통해 거칠기가 작고 표면 N vacancy가 적은 고품질의 (Al)GaN 표면을 얻을 수 있었다. 박막 연구에서는 Oxide 박막 증착 시, (Al)GaN 표면에 생성되어 계면 특성을 악화시키는 Ga2O3 생성을 막기위해 ALD AlN layer를 개발 및 적용하여 박막/(Al)GaN 계면 특성을 향상시켰다. 이로 인해 소자의 동작전류 증가 및 Dit 감소 결과를 얻을 수 있었고 스트레스에 따른 문턱전압 이동 특성의 감소로 소자의 신뢰성 또한 개선시킬 수 있었다. 이는 타 기관의 결과와 비교해도 뒤떨어지지 않는 우수한 특성을 보여주었다. 결론적으로 본 연구의 작은 플라즈마 데미지를 갖는 식각공정과 고품질 절연막 개발을 통해 우수한 특성의 GaN 전력소자를 구현할 수 있었고 향후 차세대 전력소자에 적용을 위한 가능성을 확보하였다.The Si technology for power devices have already approached its theoretical limitations due to its physical and material properties, despite the considerable efforts such as super junction MOSFET, trench gate, and insulated gate bipolar transistors. To overcome these limitations, many kinds of compound materials such as GaN, GaAs, SiC, Diamond and InP which have larger breakdown voltage and high electron velocity than Si also have been studied as future power devices. GaN has been considered as a breakthrough in power applications due to its high critical electric field, high saturation velocity and high electron mobility compared to Si, GaAs, and SiC. Especially, AlGaN/GaN heterostructure field-effect transistors (HFETs) have been considered as promising candidates for high power and high voltage applications. However, these AlGaN/GaN heterostructure field-effect transistors with the 2DEG are naturally normally-on, which makes the devices difficult to deplete the channel at zero gate bias. Among the various methods for normally-off operation of GaN devices, gate-recess method is a promising method because it can be easier to implement than other approaches and ensure normally-off operation. However, charge trapping at the interface between gate dielectric and (Al)GaN and in the gate dielectric is a big issue for recessed gate MIS-HEMTs. This problem leads to degradation of channel mobility, on-resistance and on-current of the devices. Especially, Vth hysteresis after a positive gate voltage sweep and Vth shift under a gate bias stress are important reliability challenges in gate recessed MIS-HEMTs. The scope of this work is mainly oriented to achieve high quality interface at dielectric/(Al)GaN MIS by studying low damage etching methods and the ALD process of various dielectric layers. In the etching study, various etching methods for normally-off operation have been studied. Also, etching damage was evaluated by various methods such as atomic force microscopy (AFM), photoluminescence (PL) measurements, X-ray photoelectron spectroscopy (XPS) measurements and electrical properties of the recessed schottky devices. Among the etching methods, the ALE shows the smoothest etched surface, the highest PL intensity and N/(Al+Ga) ratio of the etched AlGaN surface and the lowest leakage current of the gate recessed schottky devices. It is suggested that the ALE is a promising etching technique for normally-off gate recessed AlGaN/GaN MIS-FETs. In the study of dielectrics, excellent electrical characteristics and small threshold volt¬age drift under positive gate bias stress are achieved by employing the SiON interfacial layer. However, considerable threshold voltage drift is observed under the higher positive gate bias stress even at the devices using the SiON interfacial layer. For further improvement of interface and reliability of devices, we develop and optimize an ALD AlN as an interfacial layer to avoid the formation of poor-quality oxide at the dielectric/(Al)GaN interface. We also develop an ALD AlHfON as a bulk layer, which have a high dielectric constant and low leakage current and high breakdown field characteristics. Devices with AlN/AlON/AlHfON layer show smaller I-V hysteresis of ~10 mV than that of devices with AlON/AlHfON layer. The extracted static Ron values of devices with AlN/AlON/AlHfON and AlON/AlHfON are 1.35 and 1.69 mΩ·cm2, respectively. Besides, the effective mobility, Dit and threshold voltage instability characteristics are all improved by employing the ALD AlN. In conclusion, for high performance and improvement of reliability of normally-off AlGaN/GaN MIS-FETs, this thesis presents an etching technique for low damage etching and high-quality gate dielectric layer and suggests that the ALE and ALD AlN/AlON/AlHfON gate dielectric are very promising for the future normally-off AlGaN/GaN MIS-FETsChapter 1. Introduction 1 1.1. Backgrounds 1 1.2. Normally-off Operation in AlGaN/GaN HFETs 3 1.3. Issues and Feasible Strategies in AlGaN/GaN MIS-HFETs 11 1.4. Research Aims 15 1.5. References 17 Chapter 2. Development and Evaluation of Low Damage Etching processes 22 2.1. Introduction 22 2.2. Various Evaluation Methods of Etching Damage 24 2.3. Low-Damage Dry Etching Methods 29 2.3.1. Inductively Coupled Plasma-Reactive Ion Etching Using BCl3/Cl2 Gas Mixture 29 2.3.2. Digital Etching Using Plasma Asher and HCl 34 2.3.3. Atomic Layer Etching Using Inductively Coupled Plasma–Reactive Ion Etching System (ICP-RIE) 50 2.4. Conclusion 75 2.5. References 76 Chapter 3. SiON/HfON Gate Dielectric Layer by ALD for AlGaN/GaN MIS-FETs 80 3.1. Introduction 80 3.2. ALD Processes for SiON and HfON 83 3.3. Electrical Characteristics of ALD SiON, HfON and SiON/HfON Dual Layer on n-GaN 87 3.4. Device Characteristics of Normally-off AlGaN/GaN MIS-FETs with SiON/HfON Dual Layer 95 3.5. Conclusion 113 3.6. References 114 Chapter 4. High Quality AlN/AlON/AlHfON Gate Dielectric Layer by ALD for AlGaN/GaN MIS-FETs 120 4.1. Introduction 120 4.2. Development of ALD AlN/AlON/AlHfON Gate Stack 122 4.2.1. Process Optimization for ALD AlN 122 4.2.2. ALD AlN as an Interfacial Layer 144 4.2.3. Thickness Optimization of AlN/AlON/ AlHfON Layer 149 4.2.4. ALD AlHfON Optimization 159 4.2.5. Material Characteristics of AlN/AlON/AlHfON Layer 167 4.3. Device Characteristics of Normally-off AlGaN/GaN MIS-FETs with AlN/AlON/AlHfON Layer 171 4.4. Conclusion 182 4.5. References 183 Chapter 5. Concluding Remarks 188 Appendix. 190 A. N2 Plasma Treatment Before Dielectric Deposition 190 B. Tri-gate Normally-on/off AlGaN/GaN MIS-FETs 200 C. AlGaN/GaN Diode with MIS-gated Hybrid Anode and Edge termination 214 Abstract in Korean 219 Research Achievements 221Docto