Advanced information processing system for advanced launch system: Hardware technology survey and projections

The major goals of this effort are as follows: (1) to examine technology insertion options to optimize Advanced Information Processing System (AIPS) performance in the Advanced Launch System (ALS) environment; (2) to examine the AIPS concepts to ensure that valuable new technologies are not excluded from the AIPS/ALS implementations; (3) to examine advanced microprocessors applicable to AIPS/ALS, (4) to examine radiation hardening technologies applicable to AIPS/ALS; (5) to reach conclusions on AIPS hardware building blocks implementation technologies; and (6) reach conclusions on appropriate architectural improvements. The hardware building blocks are the Fault-Tolerant Processor, the Input/Output Sequencers (IOS), and the Intercomputer Interface Sequencers (ICIS)

A survey of carbon nanotube interconnects for energy efficient integrated circuits

This article is a review of the state-of-art carbon nanotube interconnects for Silicon application with respect to the recent literature. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) challenges with current copper interconnects, 2) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, and 3) modeling and simulation for circuit-level benchmarking and performance prediction. The focus is on the evolution of carbon nanotube interconnects from the process, theoretical modeling, and experimental characterization to on-chip interconnect applications. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a survey and informative cornerstone on carbon nanotube interconnects relevant to students and scientists belonging to a range of fields from physics, processing to circuit design

InP-based membrane photodetectors on Si photonic circuitry

The work presented in this thesis is about indium phosphide (InP) based photodetectors for use in optical interconnections on silicon (Si) integrated circuits (ICs). The motivation for this work comes from the bottleneck expected at the interconnect level for future generation electronic ICs: with the technology scaling down and the signal switching frequency increasing, three main issues are predicted for the complementary metal-oxide semiconductor (CMOS) ICs, namely signal propagation delay, power consumption and integration density. Electrical interconnects (EIs) strongly limit these characteristics and a promising solution is given by replacing EIs with optical interconnects (OIs). The implementation of intra-chip and chip-to-chip OIs requires the use of photonic integrated circuit (PIC) technology. The integration of optical sources, waveguides and detectors forming a photonic interconnect layer on top of the CMOS circuitry provides bandwidth increase, immunity to electromagnetic (EM) noise and reduction in power consumption. This solution was investigated within this work, which focuses on the detector part. InP-based membrane photodetectors were realized on InP dies bonded on Si and CMOS wafers, on top of which passive Si and Si3N4 photonic circuitry had been defined. This approach combines the advantages of high quality Si-based passive circuits with the excellent properties of InP-based components for light generation and detection. The technology used for the InP device fabrication is compatible with wafer scale processing steps, assuring compatibility towards future generation electronic ICs. The major results of this work are summarized as follows: InP membrane couplers and detectors were successfully fabricated on Si and Si3N4 photonic circuits. Experimental results show working active and passive devices, namely: passive Si photonic components (waveguides, MMIs, (de)-multiplexers), InP membrane couplers, InP-based detectors and heterogeneously integrated multiwavelength receivers. A working laser-to-detector integrated optical link on Si was successfully demonstrated. This work was carried out with the support of the European project IST-PICMOS and of the Dutch Ministry of Economic Affairs through the Smartmix Memphis project

Heterogeneous 2.5D integration on through silicon interposer

© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

Modeling and analysis of semiconductor manufacturing processes using petri nets

This thesis addresses the issues in modeling and analysis of multichip module (MCM) manufacturing processes using Petri nets. Building such graphical and mathematical models is a crucial step to understand MCM technologies and to enhance their application scope. In this thesis, the application of Petri nets is presented with top-down and bottom-up approaches. The theory of Petri nets is summarized with its basic notations and properties at first. After that, the capability of calculating and analyzing Petri nets with deterministic timing information is extended to meet the requirements of the MCM models. Then, using top-down refining and system decomposition, MCM models are built from an abstract point to concrete systems with timing information. In this process, reduction theory based on a multiple-input-single-output modules for deterministic Petri nets is applied to analyze the cycle time of Petri net models. Besides, this thesis is of significance in its use of the reduction theory which is derived for timed marked graphs - an important class of Petri nets

HIGH PERFORMANCE CLOCK DISTRIBUTION FOR HIGH-SPEED VLSI SYSTEMS

Tohoku University堀口 進課

A thermal simulation process based on electrical modeling for complex interconnect, packaging, and 3DI structures

To reduce the product development time and achieve first-pass silicon success, fast and accurate estimation of very-large-scale integration (VLSI) interconnect, packaging and 3DI (3D integrated circuits) thermal profiles has become important. Present commercial thermal analysis tools are incapable of handling very complex structures and have integration difficulties with existing design flows. Many analytical thermal models, which could provide fast estimates, are either too specific or oversimplified. This paper highlights a methodology, which exploits electrical resistance solvers for thermal simulation, to allow acquisition of thermal profiles of complex structures with good accuracy and reasonable computation cost. Moreover, a novel accurate closed-form thermal model is developed. The model allows an isotropic or anisotropic equivalent medium to replace the noncritical back-end-of-line (BEOL) regions so that the simulation complexity is dramatically reduced. Using these techniques, this paper introduces the thermal modeling of practical complex VLSI structures to facilitate thermal guideline generation. It also demonstrates the benefits of the proposed anisotropic equivalent medium approximation for real VLSI structures in terms of the accuracy and computational cost. © 2006 IEEE.published_or_final_versio