566 research outputs found

    Scaling the bulk-driven MOSFET into deca-nanometer bulk CMOS technologies

    Get PDF
    The International Technology Roadmap for Semiconductors predicts that the nominal power supply voltage, VDD, will fall to 0.7 V by the end of the bulk CMOS era. At that time, it is expected that the long-channel threshold voltage of a MOSFET, VT0, will rise to 35.5% of VDD in order to maintain acceptable off-state leakage characteristics in digital systems. Given the recent push for system-on-a-chip integration, this increasing trend in VT0/VDD poses a serious threat to the future of analog design because it causes traditional analog circuit topologies to experience progressively problematic signal swing limitations in each new process generation. To combat the process-scaling-induced signal swing limitations of analog circuitry, researchers have proposed the use of bulk-driven MOSFETs. By using the bulk terminal as an input rather than the gate, the bulk-driven MOSFET makes it possible to extend the applicability of any analog cell to extremely low power supply voltages because VT0 does not appear in the device\u27s input signal path. Since the viability of the bulk-driven technique was first investigated in a 2 um p-well process, there have been numerous reports of low-voltage analog designs incorporating bulk-driven MOSFETs in the literature - most of which appear in technologies with feature sizes larger than 0.18 um. However, as of yet, no effort has been undertaken to understand how sub-micron process scaling trends have influenced the performance of a bulk-driven MOSFET, let alone make the device more adaptable to the deca-nanometer technologies widely used in the analog realm today. Thus, to further the field\u27s understanding of the bulk-driven MOSFET, this dissertation aims to examine the implications of scaling the device into a standard 90 nm bulk CMOS process. This dissertation also describes how the major disadvantages of a bulk-driven MOSFET - i.e., its reduced intrinsic gain, its limited frequency response and its large layout area requirement - can be mitigated through modifications to the device\u27s vertical doping profile and well structure. To gauge the potency of the proposed process changes, an optimized n-type bulk-driven MOSFET has been designed in a standard 90 nm bulk CMOS process via the 2-D device simulator, ATLAS

    Advances in Solid State Circuit Technologies

    Get PDF
    This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

    Design And Characterization Of Noveldevices For New Generation Of Electrostaticdischarge (esd) Protection Structures

    Get PDF
    The technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications\u27 performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the design of robust protection structures and circuits remains challenging because ESD failure mechanisms continue to become more acute and design windows less flexible. The sensitivity of smaller devices, along with a limited understanding of the ESD phenomena and the resulting empirical approach to solving the problem have yielded time consuming, costly and unpredictable design procedures. As turnaround design cycles in new technologies continue to decrease, the traditional trial-and-error design strategy is no longer acceptable, and better analysis capabilities and a systematic design approach are essential to accomplish the increasingly difficult task of adequate ESD protection-circuit design. This dissertation presents a comprehensive design methodology for implementing custom on-chip ESD protection structures in different commercial technologies. First, the ESD topic in the semiconductor industry is revised, as well as ESD standards and commonly used schemes to provide ESD protection in ICs. The general ESD protection approaches are illustrated and discussed using different types of protection components and the concept of the ESD design window. The problem of implementing and assessing ESD protection structures is addressed next, starting from the general discussion of two design methods. The first ESD design method follows an experimental approach, in which design requirements are obtained via fabrication, testing and failure analysis. The second method consists of the technology computer aided design (TCAD)-assisted ESD protection design. This method incorporates numerical simulations in different stages of the ESD design process, and thus results in a more predictable and systematic ESD development strategy. Physical models considered in the device simulation are discussed and subsequently utilized in different ESD designs along this study. The implementation of new custom ESD protection devices and a further integration strategy based on the concept of the high-holding, low-voltage-trigger, silicon controlled rectifier (SCR) (HH-LVTSCR) is demonstrated for implementing ESD solutions in commercial low-voltage digital and mixed-signal applications developed using complementary metal oxide semiconductor (CMOS) and bipolar CMOS (BiCMOS) technologies. This ESD protection concept proposed in this study is also successfully incorporated for implementing a tailored ESD protection solution for an emerging CMOS-based embedded MicroElectroMechanical (MEMS) sensor system-on-a-chip (SoC) technology. Circuit applications that are required to operate at relatively large input/output (I/O) voltage, above/below the VDD/VSS core circuit power supply, introduce further complications in the development and integration of ESD protection solutions. In these applications, the I/O operating voltage can extend over one order of magnitude larger than the safe operating voltage established in advanced technologies, while the IC is also required to comply with stringent ESD robustness requirements. A practical TCAD methodology based on a process- and device- simulation is demonstrated for assessment of the device physics, and subsequent design and implementation of custom P1N1-P2N2 and coupled P1N1-P2N2//N2P3-N3P1 silicon controlled rectifier (SCR)-type devices for ESD protection in different circuit applications, including those applications operating at I/O voltage considerably above/below the VDD/VSS. Results from the TCAD simulations are compared with measurements and used for developing technology- and circuit-adapted protection structures, capable of blocking large voltages and providing versatile dual-polarity symmetric/asymmetric S-type current-voltage characteristics for high ESD protection. The design guidelines introduced in this dissertation are used to optimize and extend the ESD protection capability in existing CMOS/BiCMOS technologies, by implementing smaller and more robust single- or dual-polarity ESD protection structures within the flexibility provided in the specific fabrication process. The ESD design methodologies and characteristics of the developed protection devices are demonstrated via ESD measurements obtained from fabricated stand-alone devices and on-chip ESD protections. The superior ESD protection performance of the devices developed in this study is also successfully verified in IC applications where the standard ESD protection approaches are not suitable to meet the stringent area constraint and performance requirement

    Transport models and advanced numerical simulation of silicon-germanium heterojunction bipolar transistors

    Get PDF
    Applications in the emerging high-frequency markets for millimeter wave applications more and more use SiGe components for cost reasons. To support the technology effort, a reliable TCAD platform is required. The main issue in the simulation of scaled devices is related to the limitations of the physical models used to describe charge carrier transport. Inherent approximations in the HD formalism are discussed over different technology nodes, providing for the first time a complete survey of HD models capability and restrictions with scaling for simulation of SiGe HBTs. Moreover, a complete set of models for transport parameters of SiGe HBTs is reported, including low-field mobility, energy relaxation time, saturation velocity, high-field mobility and effective density of state. Implementation in a commercial device simulator is drawn and findings are compared with simulation results obtained using a standard set of models and with trustworthy results (i.e. MC and SHE simulation results and experimental data), validating proposed models and clarifying their reliability and accuracy over different technologies. Finally, electrical breakdown phenomena in SiGe HBTs are analyzed: a novel complete model for multiplication factor is reported and validated by experimental results; new M model provides an exhaustive accuracy over a wide range of collector voltages

    Advanced CMOS Process for Submicron Silicon Carbide (SiC) Device

    Get PDF
    Silicon carbide (SiC) is a wide semiconductor material with superior material properties compared to other rival materials. Due to its fewer dislocation defects than gallium nitride and its ability to form native oxides, this material possesses an advantage among wide band gap materials. Despite having several superior properties its low voltage application is less explored. CMOS is extremely important in low voltage areas and silicon is the dominant player in it for the last 50 years where scaling has contributed a major role in this flourishment. The channel length of silicon devices has reached 3 nm whereas SiC is still in the micrometer (2 ฮผm/ 1.2 ฮผm) range. So, SiC technology is still in its infancy which can be compared with silicon technology in the mid-1980s range. When the SiC devices would enter into the sub-micron and deep submicron range, proper device design in those ranges is necessary to rip the benefit of scaling. In this thesis, the SiC CMOS process available from different institutes and foundries is discussed first to understand the current state of the art. Later, low-voltage conventional SiC NMOS devices in the submicron range (2 ฮผm to 600 nm) are simulated and their key parameters and performances are analyzed. In the submicron range, one major issue in MOSFET scaling is hot carrier effects. Thus to minimize this effect, a low-doped drain (LDD) region is introduced in the conventional SiC design having a channel length of 800 nm and 600 nm. In comparison with conventional designs, LDD designs have shown better saturation current behavior, reduced threshold roll-off, reduced hot electron current density, minimized gate leakage, reduced body hole current, enhanced voltage handling capability, reduced electric field, and improved subthreshold behavior in SiC. In the end, spacer technology, dopants, doping methods, and LDD realization technique in SiC are discussed

    Advanced CMOS Process for Submicron Silicon Carbide (SiC) Device

    Get PDF
    Silicon carbide (SiC) is a wide semiconductor material with superior material properties compared to other rival materials. Due to its fewer dislocation defects than gallium nitride and its ability to form native oxides, this material possesses an advantage among wide band gap materials. Despite having several superior properties its low voltage application is less explored. CMOS is extremely important in low voltage areas and silicon is the dominant player in it for the last 50 years where scaling has contributed a major role in this flourishment. The channel length of silicon devices has reached 3 nm whereas SiC is still in the micrometer (2 ฮผm/ 1.2 ฮผm) range. So, SiC technology is still in its infancy which can be compared with silicon technology in the mid-1980s range. When the SiC devices would enter into the sub-micron and deep submicron range, proper device design in those ranges is necessary to rip the benefit of scaling. In this thesis, the SiC CMOS process available from different institutes and foundries is discussed first to understand the current state of the art. Later, low-voltage conventional SiC NMOS devices in the submicron range (2 ฮผm to 600 nm) are simulated and their key parameters and performances are analyzed. In the submicron range, one major issue in MOSFET scaling is hot carrier effects. Thus to minimize this effect, a low-doped drain (LDD) region is introduced in the conventional SiC design having a channel length of 800 nm and 600 nm. In comparison with conventional designs, LDD designs have shown better saturation current behavior, reduced threshold roll-off, reduced hot electron current density, minimized gate leakage, reduced body hole current, enhanced voltage handling capability, reduced electric field, and improved subthreshold behavior in SiC. In the end, spacer technology, dopants, doping methods, and LDD realization technique in SiC are discussed

    ๋†’์€ ์ „๋ฅ˜ ๊ตฌ๋™๋Šฅ๋ ฅ์„ ๊ฐ€์ง€๋Š” SiGe ๋‚˜๋…ธ์‹œํŠธ ๊ตฌ์กฐ์˜ ํ„ฐ๋„๋ง ์ „๊ณ„ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ

    Get PDF
    ํ•™์œ„๋…ผ๋ฌธ (๋ฐ•์‚ฌ) -- ์„œ์šธ๋Œ€ํ•™๊ต ๋Œ€ํ•™์› : ๊ณต๊ณผ๋Œ€ํ•™ ์ „๊ธฐยท์ •๋ณด๊ณตํ•™๋ถ€, 2021. 2. ๋ฐ•๋ณ‘๊ตญ.The development of very-large-scale integration (VLSI) technology has continuously demanded smaller devices to achieve high integration density for faster computing speed or higher capacity. However, in the recent complementary-metal-oxide-semiconductor (CMOS) technology, simple downsizing the dimension of metal-oxide-semiconductor field-effect transistor (MOSFET) no longer guarantees the boosting performance of IC chips. In particular, static power consumption is not reduced while device size is decreasing because voltage scaling is slowed down at some point. The increased off-current due to short-channel effect (SCE) of MOSFET is a representative cause of the difficulty in voltage scaling. To overcome these fundamental limits of MOSFET, many researchers have been looking for the next generation of FET device over the last ten years. Tunnel field-effect transistor (TFET) has been intensively studied for its steep switching characteristics. Nevertheless, the poor current drivability of TFET is the most serious obstacle to become competitive device for MOSFET. In this thesis, TFET with high current drivability in which above-mentioned problem is significantly solved is proposed. Vertically-stacked SiGe nanosheet channels are used to boost carrier injection and gate control. The fabrication technique to form highly-condensed SiGe nanosheets is introduced. TFET is fabricated with MOSFET with the same structure in the CMOS-compatible process. Both technology-computer-aided-design (TCAD) simulation and experimental results are utilized to support and examine the advantages of proposed TFET. From the perspective of the single device, the improvement in switching characteristics and current drivability are quantitatively and qualitatively analyzed. In addition, the device performance is compared to the benchmark of previously reported TFET and co-fabricated MOSFET. Through those processes, the feasibility of SiGe nanosheet TFET is verified. It is revealed that the proposed SiGe nanosheet TFET has notable steeper switching and low leakage in the low drive voltage as an alternative to conventional MOSFET.์ดˆ๊ณ ๋ฐ€๋„ ์ง‘์ ํšŒ๋กœ ๊ธฐ์ˆ ์˜ ๋ฐœ์ „์€ ๊ณ ์ง‘์ ๋„ ๋‹ฌ์„ฑ์„ ํ†ตํ•ด ๋‹จ์œ„ ์นฉ์˜ ์—ฐ์‚ฐ ์†๋„ ๋ฐ ์šฉ๋Ÿ‰ ํ–ฅ์ƒ์— ๊ธฐ์—ฌํ•  ์†Œํ˜•์˜ ์†Œ์ž๋ฅผ ๋Š์ž„์—†์ด ์š”๊ตฌํ•˜๊ณ  ์žˆ๋‹ค. ํ•˜์ง€๋งŒ ์ตœ์‹ ์˜ ์ƒ๋ณดํ˜• ๊ธˆ์†-์‚ฐํ™”๋ง‰-๋ฐ˜๋„์ฒด (CMOS) ๊ธฐ์ˆ ์—์„œ ๊ธˆ์†-์‚ฐํ™”๋ง‰-๋ฐ˜๋„์ฒด ์ „๊ณ„ ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ (MOSFET) ์˜ ๋‹จ์ˆœํ•œ ์†Œํ˜•ํ™”๋Š” ๋” ์ด์ƒ ์ง‘์ ํšŒ๋กœ์˜ ์„ฑ๋Šฅ ํ–ฅ์ƒ์„ ๋ณด์žฅํ•ด ์ฃผ์ง€ ๋ชปํ•˜๊ณ  ์žˆ๋‹ค. ํŠนํžˆ ์†Œ์ž์˜ ํฌ๊ธฐ๊ฐ€ ์ค„์–ด๋“œ๋Š” ๋ฐ˜๋ฉด ์ •์  ์ „๋ ฅ ์†Œ๋ชจ๋Ÿ‰์€ ์ „์•• ์Šค์ผ€์ผ๋ง์˜ ๋‘”ํ™”๋กœ ์ธํ•ด ๊ฐ์†Œ๋˜์ง€ ์•Š๊ณ  ์žˆ๋Š” ์ƒํ™ฉ์ด๋‹ค. MOSFET์˜ ์งง์€ ์ฑ„๋„ ํšจ๊ณผ๋กœ ์ธํ•ด ์ฆ๊ฐ€๋œ ๋ˆ„์„ค ์ „๋ฅ˜๊ฐ€ ์ „์•• ์Šค์ผ€์ผ๋ง์˜ ์–ด๋ ค์›€์„ ์ฃผ๋Š” ๋Œ€ํ‘œ์  ์›์ธ์œผ๋กœ ๊ผฝํžŒ๋‹ค. ์ด๋Ÿฌํ•œ ๊ทผ๋ณธ์ ์ธ MOSFET์˜ ํ•œ๊ณ„๋ฅผ ๊ทน๋ณตํ•˜๊ธฐ ์œ„ํ•˜์—ฌ ์ง€๋‚œ 10์—ฌ๋…„๊ฐ„ ์ƒˆ๋กœ์šด ๋‹จ๊ณ„์˜ ์ „๊ณ„ ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ ์†Œ์ž๋“ค์ด ์—ฐ๊ตฌ๋˜๊ณ  ์žˆ๋‹ค. ๊ทธ ์ค‘ ํ„ฐ๋„ ์ „๊ณ„ ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ(TFET)์€ ๊ทธ ํŠน์œ ์˜ ์šฐ์ˆ˜ํ•œ ์ „์› ํŠน์„ฑ์œผ๋กœ ๊ฐ๊ด‘๋ฐ›์•„ ์ง‘์ค‘์ ์œผ๋กœ ์—ฐ๊ตฌ๋˜๊ณ  ์žˆ๋‹ค. ๋งŽ์€ ์—ฐ๊ตฌ์—๋„ ๋ถˆ๊ตฌํ•˜๊ณ , TFET์˜ ๋ถ€์กฑํ•œ ์ „๋ฅ˜ ๊ตฌ๋™ ๋Šฅ๋ ฅ์€ MOSFET์˜ ๋Œ€์ฒด์žฌ๋กœ ์ž๋ฆฌ๋งค๊น€ํ•˜๋Š” ๋ฐ ๊ฐ€์žฅ ํฐ ๋ฌธ์ œ์ ์ด ๋˜๊ณ  ์žˆ๋‹ค. ๋ณธ ํ•™์œ„๋…ผ๋ฌธ์—์„œ๋Š” ์ƒ๊ธฐ๋œ ๋ฌธ์ œ์ ์„ ํ•ด๊ฒฐํ•  ์ˆ˜ ์žˆ๋Š” ์šฐ์ˆ˜ํ•œ ์ „๋ฅ˜ ๊ตฌ๋™ ๋Šฅ๋ ฅ์„ ๊ฐ€์ง„ TFET์ด ์ œ์•ˆ๋˜์—ˆ๋‹ค. ๋ฐ˜์†ก์ž ์œ ์ž…๊ณผ ๊ฒŒ์ดํŠธ ์ปจํŠธ๋กค์„ ํ–ฅ์ƒ์‹œํ‚ฌ ์ˆ˜ ์žˆ๋Š” ์ˆ˜์ง ์ ์ธต๋œ ์‹ค๋ฆฌ์ฝ˜์ €๋งˆ๋Š„(SiGe) ๋‚˜๋…ธ์‹œํŠธ ์ฑ„๋„์ด ์‚ฌ์šฉ๋˜์—ˆ๋‹ค. ๋˜ํ•œ, ์ œ์•ˆ๋œ TFET์€ CMOS ๊ธฐ๋ฐ˜ ๊ณต์ •์„ ํ™œ์šฉํ•˜์—ฌ MOSFET๊ณผ ํ•จ๊ป˜ ์ œ์ž‘๋˜์—ˆ๋‹ค. ํ…Œํฌ๋†€๋กœ์ง€ ์ปดํ“จํ„ฐ ์ง€์› ์„ค๊ณ„(TCAD) ์‹œ๋ฎฌ๋ ˆ์ด์…˜๊ณผ ์‹ค์ œ ์ธก์ • ๊ฒฐ๊ณผ๋ฅผ ํ™œ์šฉํ•˜์—ฌ ์ œ์•ˆ๋œ ์†Œ์ž์˜ ์šฐ์ˆ˜์„ฑ์„ ๊ฒ€์ฆํ•˜์˜€๋‹ค. ๋‹จ์œ„ CMOS ์†Œ์ž์˜ ๊ด€์ ์—์„œ, ์ „์› ํŠน์„ฑ๊ณผ ์ „๋ฅ˜ ๊ตฌ๋™ ๋Šฅ๋ ฅ์˜ ํ–ฅ์ƒ์„ ์ •๋Ÿ‰์ , ์ •์„ฑ์  ๋ฐฉ๋ฒ•์œผ๋กœ ๋ถ„์„ํ•˜์˜€๋‹ค. ๊ทธ๋ฆฌ๊ณ , ์ œ์ž‘๋œ ์†Œ์ž์˜ ์„ฑ๋Šฅ์„ ๊ธฐ์กด ์ œ์ž‘ ๋ฐ ๋ณด๊ณ ๋œ TFET ๋ฐ ํ•จ๊ป˜ ์ œ์ž‘๋œ MOSSFET๊ณผ ๋น„๊ตํ•˜์˜€๋‹ค. ์ด๋Ÿฌํ•œ ๊ณผ์ •์„ ํ†ตํ•ด, ์‹ค๋ฆฌ์ฝ˜์ €๋งˆ๋Š„ ๋‚˜๋…ธ์‹œํŠธ TFET์˜ ํ™œ์šฉ ๊ฐ€๋Šฅ์„ฑ์ด ์ž…์ฆ๋˜์—ˆ๋‹ค. ์ œ์•ˆ๋œ ์‹ค๋ฆฌ์ฝ˜์ €๋งˆ๋Š„ ๋‚˜๋…ธ์‹œํŠธ ์†Œ์ž๋Š” ์ฃผ๋ชฉํ•  ๋งŒํ•œ ์ „์› ํŠน์„ฑ์„ ๊ฐ€์กŒ๊ณ  ์ €์ „์•• ๊ตฌ๋™ ํ™˜๊ฒฝ์—์„œ ํ•œ์ธต ๋” ๋‚ฎ์€ ๋ˆ„์„ค ์ „๋ฅ˜๋ฅผ ๊ฐ€์ง์œผ๋กœ์จ ํ–ฅํ›„ MOSFET์„ ๋Œ€์ฒดํ• ๋งŒํ•œ ์ถฉ๋ถ„ํ•œ ๊ฐ€๋Šฅ์„ฑ์„ ๋ณด์—ฌ์ฃผ์—ˆ๋‹ค.Chapter 1 Introduction 1 1.1. Power Crisis of Conventional CMOS Technology 1 1.2. Tunnel Field-Effect Transistor (TFET) 6 1.3. Feasibility and Challenges of TFET 9 1.4. Scope of Thesis 11 Chapter 2 Device Characterization 13 2.1. SiGe Nanosheet TFET 13 2.2. Device Concept 15 2.3. Calibration Procedure for TCAD simulation 17 2.4. Device Verification with TCAD simulation 21 Chapter 3 Device Fabrication 31 3.1. Fabrication Process Flow 31 3.2. Key Processes for SiGe Nanosheet TFET 33 3.2.1. Key Process 1 : SiGe Nanosheet Formation 34 3.2.2. Key Process 2 : Source/Drain Implantation 41 3.2.3. Key Process 3 : High-ฮบ/Metal gate Formation 43 Chapter 4 Results and Discussion 53 4.1. Measurement Results 53 4.2. Analysis of Device Characteristics 56 4.2.1. Improved Factors to Performance in SiGe Nanosheet TFET 56 4.2.2. Performance Comparison with SiGe Nanosheet MOSFET 62 4.3. Performance Evaluation through Benchmarks 64 4.4. Optimization Plan for SiGe nanosheet TFET 66 4.4.1. Improvement of Quality of Gate Dielectric 66 4.4.2. Optimization of Doping Junction at Source 67 Chapter 5 Conclusion 71 Bibliography 73 Abstract in Korean 81 List of Publications 83Docto
    • โ€ฆ
    corecore