Analysis And Design Optimization Of Multiphase Converter

Future microprocessors pose many challenges to the power conversion techniques. Multiphase synchronous buck converters have been widely used in high current low voltage microprocessor application. Design optimization needs to be carefully carried out with pushing the envelope specification and ever increasing concentration towards power saving features. In this work, attention has been focused on dynamic aspects of multiphase synchronous buck design. The power related issues and optimizations have been comprehensively investigated in this paper. In the first chapter, multiphase DC-DC conversion is presented with background application. Adaptive voltage positioning and various nonlinear control schemes are evaluated. Design optimization are presented to achieve best static efficiency over the entire load range. Power loss analysis from various operation modes and driver IC definition are studied thoroughly to better understand the loss terms and minimize the power loss. Load adaptive control is then proposed together with parametric optimization to achieve optimum efficiency figure. New nonlinear control schemes are proposed to improve the transient response, i.e. load engage and load release responses, of the multiphase VR in low frequency repetitive transient. Drop phase optimization and PWM transition from long tri-state phase are presented to improve the smoothness and robustness of the VR in mode transition. During high frequency repetitive transient, the control loop should be optimized and nonlinear loop should be turned off. Dynamic current sharing are thoroughly studied in chapter 4. The output impedance of the multiphase v synchronous buck are derived to assist the analysis. Beat frequency is studied and mitigated by proposing load frequency detection scheme by turning OFF the nonlinear loop and introducing current protection in the control loop. Dynamic voltage scaling (DVS) is now used in modern Multi-Core processor (MCP) and multiprocessor System-on-Chip (MPSoC) to reduce operational voltage under light load condition. With the aggressive motivation to boost dynamic power efficiency, the design specification of voltage transition (dv/dt) for the DVS is pushing the physical limitation of the multiphase converter design and the component stress as well. In this paper, the operation modes and modes transition during dynamic voltage transition are illustrated. Critical dead-times of driver IC design and system dynamics are first studied and then optimized. The excessive stress on the control MOSFET which increases the reliability concern is captured in boost mode operation. Feasible solutions are also proposed and verified by both simulation and experiment results. CdV/dt compensation for removing the AVP effect and novel nonlinear control scheme for smooth transition are proposed for dealing with fast voltage positioning. Optimum phase number control during dynamic voltage transition is also proposed and triggered by voltage identification (VID) delta to further reduce the dynamic loss. The proposed schemes are experimentally verified in a 200 W six phase synchronous buck converter. Finally, the work is concluded. The references are listed

Low Voltage Regulator Modules and Single Stage Front-end Converters

Evolution in microprocessor technology poses new challenges for supplying power to these devices. To meet demands for faster and more efficient data processing, modem microprocessors are being designed with lower voltage implementations. More devices will be packed on a single processor chip and the processors will operate at higher frequencies, exceeding 1GHz. New high-performance microprocessors may require from 40 to 80 watts of power for the CPU alone. Load current must be supplied with up to 30A/µs slew rate while keeping the output voltage within tight regulation and response time tolerances. Therefore, special power supplies and Voltage Regulator Modules (VRMs) are needed to provide lower voltage with higher current and fast response. In the part one (chapter 2,3,4) of this dissertation, several low-voltage high-current VRM technologies are proposed for future generation microprocessors and ICs. The developed VRMs with these new technologies have advantages over conventional ones in terms of efficiency, transient response and cost. In most cases, the VRMs draw currents from DC bus for which front-end converters are used as a DC source. As the use of AC/DC frond-end converters continues to increase, more distorted mains current is drawn from the line, resulting in lower power factor and high total harmonic distortion. As a branch of active Power factor correction (PFC) techniques, the single-stage technique receives particular attention because of its low cost implementation. Moreover, with continuously demands for even higher power density, switching mode power supply operating at high-frequency is required because at high switching frequency, the size and weight of circuit components can be remarkably reduced. To boost the switching frequency, the soft-switching technique was introduced to alleviate the switching losses. The part two (chapter 5,6) of the dissertation presents several topologies for this front-end application. The design considerations, simulation results and experimental verification are discussed

High Slew Rate High-efficiency Dc-dc Converter

Active transient voltage compensator (ATVC) has been proposed to improve VR transient response at high slew rate load, which engages in transient periods operating in MHZ to inject high slew rate current in step up load and recovers energy in step down load. Main VR operates in low switching frequency mainly providing DC current. Parallel ATVC has largely reduced conduction and switching losses. Parallel ATVC also reduces the number of VR bulk capacitors. Combined linear and adaptive nonlinear control has been proposed to reduce delay times in the actual controller, which injects one nonlinear signal in transient periods and simplifies the linear controller design. Switching mode current compensator with nonlinear control in secondary side is proposed to eliminate the effect of opotocoupler, which reduces response times and simplifies the linear controller design in isolated DC-DC converters. A novel control method has been carried out in two-stage isolated DC-DC converter to simplify the control scheme and improve the transient response, allowing for high duty cycle operation and large step-down voltage ratio with high efficiency. A balancing winding network composed of small power rating components is used to mitigate the double pole-zero effect in complementary-controlled isolated DC-DC converter, which simplifies the linear control design and improves the transient response without delay time. A parallel post regulator (PPR) is proposed for wide range input isolated DC-DC converter with secondary side control, which provides small part of output power and most of them are handled by unregulated rectifier with high efficiency. PPR is easy to achieve ZVS in primary side both in wide range input and full load range due to 0.5 duty cycle. PPR has reduced conduction loss and reduced voltage rating in the secondary side due to high turn ratio transformer, resulting in up to 8 percent efficiency improvement in the prototype compared to conventional methods

An Effect of Output Capacitor ESL on Hysteretic PLL Controlled Multiphase Buck Converter

This paper provides analysis of output capacitor effects to phase stability of a hysteretic mode controlled buck converter. The hysteretic control method is a simple and fast control technique for switched-mode converters, but the hysteresis control is not oscillator referenced. It results in difficulty to achieve stable switching phase and frequency. In recent papers, the authors propose a use of phase locked loops (PLL) to permit interleaved multiphase operation where each voltage regulator (VR) module is coupled together via output node and leads to a strong loop interaction. In this work analysis of this interaction is studied by Matlab Simulink simulations and a new solution how to partially suppress this effect is given. The proposed method confirms the theoretical analysis

Voltage regulation of a series stacked system of digital loads by differential power processing

A modern high-end multi-core microprocessor has very stringent power supply requirements. It can draw hundreds of amperes of current at supply voltages as low as 0.8 V. As the supply voltages keep decreasing, the power delivery to meet the supply requirements is becoming increasingly difficult and inefficient. However, the presence of multiple cores in the microprocessor offers us a way to power it at a higher voltage by series-stacking the cores. Differential power processing has been shown to be an efficient way to series-stack server loads. In this work we study the dynamics of the element-to-element DPP topology implemented with bi-directional buck-boost converters. Some of its dynamic drawbacks are pointed out and a topological modification to counter those drawbacks is proposed. We then develop a linear control to regulate processor core voltages in a series stack of 4 cores. A hysteretic control to accommodate light load modes in the bi-directional regulating converters is also discussed. Both the linear and the hysteretic controller are implemented successfully in hardware and efficiency improvement due to light-load modes is demonstrated

Transient Response Improvement For Multi-phase Voltage Regulators

Next generation microprocessor (Vcore) requirements for high current slew rates and fast transient response together with low output voltage have posed great challenges on voltage regulator (VR) design . Since the debut of Intel 80X86 series, CPUs have greatly improved in performance with a dramatic increase on power consumption. According to the latest Intel VR11 design guidelines , the operational current may ramp up to 140A with typical voltages in the 1.1V to 1.4V range, while the slew rate of the transient current can be as high as 1.9A/ns [1, 2]. Meanwhile, the transient-response requirements are becoming stringer and stringer. This dissertation presents several topics on how to improve transient response for multi-phase voltage regulators. The Adaptive Modulation Control (AMC) is a type of non-linear control method which has proven to be effective in achieving high bandwidth designs as well as stabilizing the control loop during large load transients. It adaptively adjusts control bandwidth by changing the modulation gain, depending on different load conditions. With the AMC, a multiphase voltage regulator can be designed with an aggressively high bandwidth. When in heavy load transients where the loop could be potentially unstable, the bandwidth is lowered. Therefore, the AMC provides an optimal means for robust high-bandwidth design with excellent transient performance. The Error Amplifier Voltage Positioning (EAVP) is proposed to improve transient response by removing undesired spikes and dips after initial transient response. The EAVP works only in a short period of time during transient events without modifying the power stage and changing the control loop gain. It facilitates the error amplifier voltage recovering during transient events, achieving a fast settling time without impact on the whole control loop. Coupled inductors are an emerging topology for computing power supplies as VRs with coupled inductors show dynamic and steady-state advantages over traditional VRs. This dissertation first covers the coupling mechanism in terms of both electrical and reluctance modeling. Since the magnetizing inductance plays an important role in the coupled-inductor operation, a unified State-Space Averaging model is then built for a two-phase coupled-inductor voltage regulator. The DC solutions of the phase currents are derived in order to show the impact of the magnetizing inductance on phase current balancing. A small signal model is obtained based on the state-space-averaging model. The effects of magnetizing inductance on dynamic performance are presented. The limitations of conventional DCR current-sensing for coupled inductors are addressed. Traditional inductor DCR current sensing topology and prior arts fail to extract phase currents for coupled inductors. Two new DCR current sensing topologies for coupled inductors are presented in this dissertation. By implementation of simple RC networks, the proposed topologies can preserve the coupling effect between phases. As a result, accurate phase inductor currents and total current can be sensed, resulting in excellent current and voltage regulation. While coupled-inductor topologies are showing advantages in transient response and are becoming industry practices, they are suffering from low steady-state operating efficiency. Motivated by the challenging transient and efficiency requirements, this dissertation proposes a Full Bridge Coupled Inductor (FBCI) scheme which is able to improve transient response as well as savor high efficiency at (a) steady state. The FBCI can change the circuit configuration under different operational conditions. Its flexible topology is able to optimize both transient response and steady-state efficiency. The flexible core configuration makes implementation easy and clear of IP issues. A novel design methodology for planar magnetics based on numerical analysis of electromagnetic fields is offered and successfully applied to the design of low-voltage high power density dc-dc converters. The design methodology features intense use of FEM simulation. The design issues of planar magnetics, including loss mechanism in copper and core, winding design on PCB, core selections, winding arrangements and so on are first reviewed. After that, FEM simulators are introduced to numerically compute the core loss and winding loss. Consequently, a software platform for magnetics design is established, and optimized magnetics can then be achieved. Dynamic voltage scaling (DVS) technology is a common industry practice in optimizing power consumption of microprocessors by dynamically altering the supply voltage under different operational modes, while maintaining the performance requirements. During DVS operation, it is desirable to position the output voltage to a new level commanded by the microprocessor (CPU) with minimum delay. However, voltage deviation and slow settling time usually exist due to large output capacitance and compensation delay in voltage regulators. Although optimal DVS can be achieved by modifying the output capacitance and compensation, this method is limited by constraints from stringent static and dynamic requirements. In this dissertation, the effects of output capacitance and compensation network on DVS operation are discussed in detail. An active compensator scheme is then proposed to ensure smooth transition of the output voltage without change of power stage and compensation during DVS. Simulation and experimental results are included to demonstrate the effectiveness of the proposed scheme

An Overview of Fully Integrated Switching Power Converters Based on Switched-Capacitor versus Inductive Approach and Their Advanced Control Aspects

This paper reviews and discusses the state of the art of integrated switched-capacitor and integrated inductive power converters and provides a perspective on progress towards the realization of efficient and fully integrated DC–DC power conversion. A comparative assessment has been presented to review the salient features in the utilization of transistor technology between the switched-capacitor and switched inductor converter-based approaches. First, applications that drive the need for integrated switching power converters are introduced, and further implementation issues to be addressed also are discussed. Second, different control and modulation strategies applied to integrated switched-capacitor (voltage conversion ratio control, duty cycle control, switching frequency modulation, Ron modulation, and series low drop out) and inductive converters (pulse width modulation and pulse frequency modulation) are then discussed. Finally, a complete set of integrated power converters are related in terms of their conditions and operation metrics, thereby allowing a categorization to provide the suitability of converter technologies

Fixed-switching frequency sliding mode control applied to power converters

The application of the sliding mode control in power converters has a well-known inconvenient from the practical point of view, which is to obtain fixed switching frequency implementations. This thesis deals with the development of a hysteresis band controller in charge of fixing the switching frequency of a sliding motion in power electronics applications. The proposed control measures the switching period of the control signal and modifies the hysteresis band of the comparator in order to regulate the switching frequency of the sliding motion. The proposed structure becomes in an additional control loop aside from main control loop implementing the sliding mode controller. In the first part of the thesis, the switching frequency control system is modelled and a design criteria for the control parameters are derived for guaranteeing closed loop stability, under different approaches and taking into account the most expectable working scenarios. In the second part of the thesis, the proposed strategies are applied to several power converters prototypes. Specifically, DC-to-DC and DC-to-AC power converters are built and the experimental results are shown. In this part, the strategies used for implementing the controllers are also deeply discussed.La aplicación del control en modo deslizante en el ámbito de la electrónica de potencia presente una problemática ampliamente conocida, obtener aplicaciones a frecuencia fija de operación. Es esta tesis se estudia el desarrollo de un comparador con histéresis variable encargado de regular el periodo de conmutación de controladores bajo regímenes deslizantes en convertidores de potencia. La estructura propuesta mide el periodo de conmutación de la señal de control y actualiza, de manera adecuada, la banda de histéresis del comparador a tal fin de regular la frecuencia de conmutación al valor deseado. La solución propuesta forma un segundo lazo de control, además del lazo de control principal que implementa el controlador en modo deslizante. En la primera parte de la tesis, éste segundo lazo es modelado, haciendo posible el estudio de las condiciones de estabilidad bajo realizaciones en tiempo continuo y en tiempo discreto. Además, se estudian las condiciones típicas de trabajo de los controladores utilizados en convertidores de potencia, como son los esquemas de regulación y de seguimiento de señales variantes en el tiempo. La segunda parte de la tesis se centra en evaluar, de manera experimental, los desarrollos teóricos de los controladores propuestos en convertidores de potencia. Concretamente, en la tesis se presentan los resultados experimentales obtenidos con diversos convertidores DC-DC y DC-AC. Adicionalmente, las metodologías y técnicas de implementación de los controladores son, de igual modo, ampliamente descritas.Postprint (published version

Fixed-switching frequency sliding mode control applied to power converters

The application of the sliding mode control in power converters has a well-known inconvenient from the practical point of view, which is to obtain fixed switching frequency implementations. This thesis deals with the development of a hysteresis band controller in charge of fixing the switching frequency of a sliding motion in power electronics applications. The proposed control measures the switching period of the control signal and modifies the hysteresis band of the comparator in order to regulate the switching frequency of the sliding motion. The proposed structure becomes in an additional control loop aside from main control loop implementing the sliding mode controller. In the first part of the thesis, the switching frequency control system is modelled and a design criteria for the control parameters are derived for guaranteeing closed loop stability, under different approaches and taking into account the most expectable working scenarios. In the second part of the thesis, the proposed strategies are applied to several power converters prototypes. Specifically, DC-to-DC and DC-to-AC power converters are built and the experimental results are shown. In this part, the strategies used for implementing the controllers are also deeply discussed.La aplicación del control en modo deslizante en el ámbito de la electrónica de potencia presente una problemática ampliamente conocida, obtener aplicaciones a frecuencia fija de operación. Es esta tesis se estudia el desarrollo de un comparador con histéresis variable encargado de regular el periodo de conmutación de controladores bajo regímenes deslizantes en convertidores de potencia. La estructura propuesta mide el periodo de conmutación de la señal de control y actualiza, de manera adecuada, la banda de histéresis del comparador a tal fin de regular la frecuencia de conmutación al valor deseado. La solución propuesta forma un segundo lazo de control, además del lazo de control principal que implementa el controlador en modo deslizante. En la primera parte de la tesis, éste segundo lazo es modelado, haciendo posible el estudio de las condiciones de estabilidad bajo realizaciones en tiempo continuo y en tiempo discreto. Además, se estudian las condiciones típicas de trabajo de los controladores utilizados en convertidores de potencia, como son los esquemas de regulación y de seguimiento de señales variantes en el tiempo. La segunda parte de la tesis se centra en evaluar, de manera experimental, los desarrollos teóricos de los controladores propuestos en convertidores de potencia. Concretamente, en la tesis se presentan los resultados experimentales obtenidos con diversos convertidores DC-DC y DC-AC. Adicionalmente, las metodologías y técnicas de implementación de los controladores son, de igual modo, ampliamente descritas

Low Power DC-DC Converters and a Low Quiescent Power High PSRR Class-D Audio Amplifier

High-performance DC-DC voltage converters and high-efficient class-D audio amplifiers are required to extend battery life and reduce cost in portable electronics. This dissertation focuses on new system architectures and design techniques to reduce area and minimize quiescent power while achieving high performance. Experimental results from prototype circuits to verify theory are shown. Firstly, basics on low drop-out (LDO) voltage regulators are provided. Demand for system-on-chip solutions has increased the interest in LDO voltage regulators that do not require a bulky off-chip capacitor to achieve stability, also called capacitor- less LDO (CL-LDO) regulators. Several architectures have been proposed; however, comparing these reported architectures proves difficult, as each has a distinct process technology and specifications. This dissertation compares CL-LDOs in a unified manner. Five CL-LDO regulator topologies were designed, fabricated, and tested under common design conditions. Secondly, fundamentals on DC-DC buck converters are presented and area reduction techniques for the external output filter, power stage, and compensator are proposed. A fully integrated buck converter using standard CMOS technology is presented. The external output filter has been fully-integrated by increasing the switching frequency up to 45 MHz. Moreover, a monolithic single-input dual-output buck converter is proposed. This architecture implements only three switches instead of the four switches used in conventional solutions, thus potentially reducing area in the power stage through proper design of the power switches. Lastly, a monolithic PWM voltage mode buck converter with compact Type-III compensation is proposed. This compensation scheme employs a combination of Gm-RC and Active-RC techniques to reduce the area of the compensator, while maintaining low quiescent power consumption and fast transient response. The proposed compensator reduces area by more than 45% when compared to an equivalent conventional Type-III compensator. Finally, basics on class-D audio amplifiers are presented and a clock-free current controlled class-D audio amplifier using integral sliding mode control is proposed. The proposed amplifier achieves up to 82 dB of power supply rejection ratio and a total harmonic distortion plus noise as low as 0.02%. The IC prototype’s controller consumes 30% less power than those featured in recently published works