Selected papers from the symposium on integrated circuits and systems design (SBCCI 2011)

1 Dipartimento di Ingegneria dell'Informazione, Universita Politecnica delle Marche, Via Brecce Bianche, Ancona, Italy 2 Centro de Engenharia Eletrica e Informatica, Universidade Federal de Campina Grande, Brazil 3 Institute for Information Processing Technology (ITIV), Karlsruhe Institute of Technology (KIT), 76131 Karlsruhe, Germany 4Centro de Informatica, Universidade Federal da Paraiba, Joao Pessoa, Brazi

MOSFET zero-temperature-coefficient (ZTC) effect modeling anda analysis for low thermal sensitivity analog applications

Continuing scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies brings more integration and consequently temperature variation has become more aggressive into a single die. Besides, depending on the application, room ambient temperature may also vary. Therefore, procedures to decrease thermal dependencies of eletronic circuit performances become an important issue to include in both digital and analog Integrated Circuits (IC) design flow. The main purpose of this thesis is to present a design methodology for a typical CMOS Analog design flow to make circuits as insensitivity as possible to temperature variation. MOSFET Zero Temperature Coefficient (ZTC) and Transconductance Zero Temperature Coefficient (GZTC) bias points are modeled to support it. These are used as reference to deliver a set of equations that explains to analog designers how temperature will change transistor operation and hence the analog circuit behavior. The special bias conditions are analyzed using a MOSFET model that is continuous from weak to strong inversion, and both are proven to occur always from moderate to strong inversion operation in any CMOS fabrication process. Some circuits are designed using proposed methodology: two new ZTC-based current references, two new ZTC-based voltage references and four classical Gm-C circuits biased at GZTC bias point (or defined here as GZTC-C filters). The first current reference is a Self-biased CMOS Current Reference (ZSBCR), which generates a current reference of 5 A. It is designed in an 180 nm process, operating with a supply voltage from 1.4V to 1.8 V and occupying around 0:010mm2 of silicon area. From circuit simulations the reference shows an effective temperature coefficient (TCeff ) of 15 ppm/oC from 45 to +85oC, and a fabrication process sensitivity of = = 4:5%, including average process and local mismatch. Simulated power supply sensitivity is estimated around 1%/V. The second proposed current reference is a Resistorless Self-Biased ZTC Switched Capacitor Current Reference (ZSCCR). It is also designed in an 180 nm process, resulting a reference current of 5.88 A under a supply voltage of 1.8 V, and occupying a silicon area around 0:010mm2. Results from circuit simulation show an TCeff of 60 ppm/oC from -45 to +85 oC and a power consumption of 63 W. The first proposed voltage reference is an EMI Resisting MOSFET-Only Voltage Reference (EMIVR), which generates a voltage reference of 395 mV. The circuit is designed in a 130 nm process, occupying around 0.0075 mm2 of silicon area while consuming just 10.3 W. Post-layout simulations present a TCeff of 146 ppm/oC, for a temperature range from 55 to +125oC. An EMI source of 4 dBm (1 Vpp amplitude) injected into the power supply of circuit, according to Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of -1.7 % and 35.8m Vpp, respectively. The second proposed voltage reference is a 0.5V Schottky-based Voltage Reference (SBVR). It provides three voltage reference outputs, each one utilizing different threshold voltage MOSFETs (standard-VT , low-VT , and zero-VT ), all available in adopted 130 nm CMOS process. This design results in three different and very low reference voltages: 312, 237, and 51 mV, presenting a TCeff of 214, 372, and 953 ppm/oC in a temperature range from -55 to 125oC, respectively. It occupies around 0.014 mm2 of silicon area for a total power consumption of 5.9 W. Lastly, a few example Gm-C circuits are designed using GZTC technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits are simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.A contínua miniaturização das tecnologias CMOS oferece maior capacidade de integração e, consequentemente, as variações de temperatura dentro de uma pastilha de silício têm se apresentado cada vez mais agressivas. Ademais, dependendo da aplicação, a temperatura ambiente a qual o CHIP está inserido pode variar. Dessa maneira, procedimentos para diminuir o impacto dessas variações no desempenho do circuito são imprescindíveis. Tais métodos devem ser incluídos em ambos fluxos de projeto CMOS, analógico e digital, de maneira que o desempenho do sistema se mantenha estável quando a temperatura oscilar. A ideia principal desta dissertação é propor uma metodologia de projeto CMOS analógico que possibilite circuitos com baixa dependência térmica. Como base fundamental desta metodologia, o efeito de coeficiente térmico nulo no ponto de polarização da corrente de dreno (ZTC) e da transcondutância (GZTC) do MOSFET são analisados e modelados. Tal modelamento é responsável por entregar ao projetista analógico um conjunto de equações que esclarecem como a temperatura influencia o comportamento do transistor e, portanto, o comportamento do circuito. Essas condições especiais de polarização são analisadas usando um modelo de MOSFET que é contínuo da inversão fraca para forte. Além disso, é mostrado que as duas condições ocorrem em inversão moderada para forte em qualquer processo CMOS. Algumas aplicações são projetadas usando a metodologia proposta: duas referências de corrente baseadas em ZTC, duas referências de tensão baseadas em ZTC, e quatro circuitos gm-C polarizados em GZTC. A primeira referência de corrente é uma Corrente de Referência CMOS Auto-Polarizada (ZSBCR), que gera uma referência de 5uA. Projetada em CMOS 180 nm, a referência opera com uma tensão de alimentação de 1.4 à 1.8 V, ocupando uma área em torno de 0:010mm2. Segundo as simulações, o circuito apresenta um coeficiente de temperatura efetivo (TCeff ) de 15 ppm/oC para -45 à +85 oC e uma sensibilidade à variação de processo de = = 4:5% incluindo efeitos de variabilidade dos tipos processo e descasamento local. A sensibilidade de linha encontrada nas simulações é de 1%=V . A segunda referência de corrente proposta é uma Corrente de Referência Sem Resistor Auto-Polarizada com Capacitor Chaveado (ZSCCR). O circuito é projetado também em 180 nm, resultando em uma corrente de referência de 5.88 A, para uma tensão de alimentação de 1.8 V, e ocupando uma área de 0:010mm2. Resultados de simulações mostram um TCeff de 60 ppm/oC para um intervalo de temperatura de -45 à +85 oC e um consumo de potência de 63 W. A primeira referência de tensão proposta é uma Referência de Tensão resistente à pertubações eletromagnéticas contendo apenas MOSFETs (EMIVR), a qual gera um valor de referência de 395 mV. O circuito é projetado no processo CMOS 130 nm, ocupando em torno de 0.0075 mm2 de área de silício, e consumindo apenas 10.3 W. Simulações pós-leiaute apresentam um TCeff de 146 ppm/oC, para um intervalo de temperatura de 55 à +125oC. Uma fonte EMI de 4 dBm (1 Vpp de amplitude) aplicada na alimentação do circuito, de acordo com o padrão Direct Power Injection (DPI), resulta em um máximo de desvio DC e ondulação Pico-à-Pico de -1.7 % e 35.8m Vpp, respectivamente. A segunda referência de tensão é uma Tensão de Referência baseada em diodo Schottky com 0.5V de alimentação (SBVR). Ela gera três saídas, cada uma utilizando MOSFETs com diferentes tensões de limiar (standard-VT , low-VT , e zero-VT ). Todos disponíveis no processo adotado CMOS 130 nm. Este projeto resulta em três diferentes voltages de referências: 312, 237, e 51 mV, apresentando um TCeff de 214, 372, e 953 ppm/oC no intervalo de temperatura de -55 à 125oC, respectivamente. O circuito ocupa em torno de 0.014 mm2, consumindo um total de 5.9 W. Por último, circuitos gm-C são projetados usando o conceito GZTC: um emulador de resistor, um inversor de impedância, um filtro de primeira ordem e um filtro de segunda ordem. Os circuitos também são simulados no processo CMOS 130 nm, resultando em uma melhora na estabilidade térmica dos seus principais parâmetros, indo de 27 à 53 ppm/°C

A new high speed charge and high efficiency Li-Ion battery charger interface using pulse control technique

A new Li-Ion battery charger interface (BCI) using pulse control (PC) technique is designed and analyzed in this paper. Thanks to the use of PC technique, the main standards of the Li-Ion battery charger, i.e. fast charge, small surface area and high efficiency, are achieved. The proposed charger achieves full charge in forty-one minutes passing by the constant current (CC) charging mode which also included the start-up and the constant voltage mode (CV) charging mode. It designed, simulated and layouted which occupies a small size area 0.1 mm2 by using Taiwan Semiconductor Manufacturing Company 180 nm complementary metal oxide semi-conductor technology (TSMC 180 nm CMOS) technology in Cadence Virtuoso software. The battery voltage VBAT varies between 2.9 V to 4.35 V and the maximum battery current IBAT is 2.1 A in CC charging mode, according to a maximum input voltage VIN equal 5 V. The maximum charging efficiency reaches 98%

Digital-Based Analog Processing in Nanoscale CMOS ICs for IoT Applications

L'abstract è presente nell'allegato / the abstract is in the attachmen

Digital-based analog processing in nanoscale CMOS ICs for IoT applications

The Internet-of-Things (IoT) concept has been opening up a variety of applications, such as urban and environmental monitoring, smart health, surveillance, and home automation. Most of these IoT applications require more and more power/area efficient Complemen tary Metal–Oxide–Semiconductor (CMOS) systems and faster prototypes (lower time-to market), demanding special modifications in the current IoT design system bottleneck: the analog/RF interfaces. Specially after the 2000s, it is evident that there have been significant improvements in CMOS digital circuits when compared to analog building blocks. Digital circuits have been taking advantage of CMOS technology scaling in terms of speed, power consump tion, and cost, while the techniques running behind the analog signal processing are still lagging. To decrease this historical gap, there has been an increasing trend in finding alternative IC design strategies to implement typical analog functions exploiting Digital in-Concept Design Methodologies (DCDM). This idea of re-thinking analog functions in digital terms has shown that Analog ICs blocks can also avail of the feature-size shrinking and energy efficiency of new technologies. This thesis deals with the development of DCDM, demonstrating its compatibility for Ultra-Low-Voltage (ULV) and Power (ULP) IoT applications. This work proves this state ment through the proposing of new digital-based analog blocks, such as an Operational Transconductance Amplifiers (OTAs) and an ac-coupled Bio-signal Amplifier (BioAmp). As an initial contribution, for the first time, a silicon demonstration of an embryonic Digital-Based OTA (DB-OTA) published in 2013 is exhibited. The fabricated DB-OTA test chip occupies a compact area of 1,426 µm2 , operating at supply voltages (VDD) down to 300 mV, consuming only 590 pW while driving a capacitive load of 80pF. With a Total Harmonic Distortion (THD) lower than 5% for a 100mV input signal swing, its measured small-signal figure of merit (FOMS) and large-signal figure of merit (FOML) are 2,101 V −1 and 1,070, respectively. To the best of this thesis author’s knowledge, this measured power is the lowest reported to date in OTA literature, and its figures of merit are the best in sub-500mV OTAs reported to date. As the second step, mainly due to the robustness limitation of previous DB-OTA, a novel calibration-free digital-based topology is proposed, named here as Digital OTA (DIG OTA). A 180-nm DIGOTA test chip is also developed exhibiting an area below the 1000 µm2 wall, 2.4nW power under 150pF load, and a minimum VDD of 0.25 V. The proposed DIGOTA is more digital-like compared with DB-OTA since no pseudo-resistor is needed. As the last contribution, the previously proposed DIGOTA is then used as a building block to demonstrate the operation principle of power-efficient ULV and ultra-low area (ULA) fully-differential, digital-based Operational Transconductance Amplifier (OTA), suitable for microscale biosensing applications (BioDIGOTA) such as extreme low area Body Dust. Measured results in 180nm CMOS confirm that the proposed BioDIGOTA can work with a supply voltage down to 400 mV, consuming only 95 nW. The BioDIGOTA layout occupies only 0.022 mm2 of total silicon area, lowering the area by 3.22X times compared to the current state of the art while keeping reasonable system performance, such as 7.6 Noise Efficiency Factor (NEF) with 1.25 µVRMS input-referred noise over a 10 Hz bandwidth, 1.8% of THD, 62 dB of the common-mode rejection ratio (CMRR) and 55 dB of power supply rejection ratio (PSRR). After reviewing the current DCDM trend and all proposed silicon demonstrations, the thesis concludes that, despite the current analog design strategies involved during the analog block development

Energy efficiency analysis in wireless communication systems with reconfigurable RF

Orientador: Prof. Dr. André Augusto MarianoCoorientador: Prof. Dr. Glauber Gomes de Oliveira BranteTese (doutorado) - Universidade Federal do Paraná, Setor de Tecnologia, Programa de Pós-Graduação em Engenharia Elétrica. Defesa : Curitiba, 28/05/2021Inclui referências: p. 74-84Área de concentração: Sistemas EletrônicosResumo: Alta eficiˆencia energ'etica (EE) 'e crucial para aplicac¸ ˜oes da Internet das Coisas que operam remotamente, uma vez que os n'os sem fio s˜ao tipicamente alimentados por bateria. Diferentes t'ecnicas de diversidade espacial tais com o uso de m'ultiplas antenas (MIMO) nos n'os do transmissor e receptor, bem como o uso de comunicac¸ ˜ao cooperativa podem ser exploradas para melhorar a EE. Al'em disso, o uso de transceptores de r'adio frequˆencia (RF) reconfigur'aveis s˜ao considerados uma soluc¸ ˜ao interessante para sistemas com restric¸ ˜ao de energia, pois permitem alterar o seu ponto de funcionamento, bem como o seu consumo de potˆencia, adaptando-se aos diferentes requisitos de comunicac¸ ˜ao. Nessa tese, uma nova abordagem para economizar energia inclui no modelo do sistema de comunicac¸ ˜ao o uso de transceptores de RF reconfigur'aveis. Mais especificamente, os componentes envolvidos em nossa estrutura de otimizac¸ ˜ao de consumo de potˆencia s˜ao o amplificador de potˆencia (PA) no transmissor e o amplificador de baixo ru'?do (LNA) no receptor. Nosso objetivo 'e mostrar que os circuitos de RF baseados em operac¸ ˜oes mult'?modo podem melhorar significativamente a EE. Assim, realizamos uma selec¸ ˜ao conjunta dos melhores modos de operac¸ ˜ao para os circuitos do PA e do LNA para diferentes esquemas de transmiss˜ao em dois cen'arios de rede: i) comunicac¸ ˜ao n˜ao-cooperativa em que os n'os s˜ao equipados com m'ultiplas antenas, para a qual consideramos a selec¸ ˜ao de antenas (AS) e a decomposic¸ ˜ao por valores singulares (SVD); e ii) comunicac¸ ˜ao cooperativa em que os n'os s˜ao equipados com uma 'unica antena, para a qual consideramos decodificac¸ ˜ao incremental e encaminha (IDF) por rel'e. Em nosso primeiro cen'ario proposto, comparamos os circuitos reconfigur 'aveis do PA e do LNA com amplificadores de RF n˜ao-reconfigur'aveis do estado-da-arte dispon'?veis na literatura. Nesta comparac¸ ˜ao, ao explorar as caracter'?sticas dos amplificadores reconfigur'aveis de RF, mostramos uma melhora de EE de mais de 40% em distˆancias curtas para as comunicac¸ ˜oes MIMO. Ao comparar os esquemas MIMO, a t'ecnica AS apresenta melhor desempenho para distˆancias mais curtas, enquanto que o SVD permite transmiss˜oes mais longas, pois explora todas as antenas dispon'?veis. Al'em disso, a otimizac¸ ˜ao da eficiˆencia espectral contribui para aumentar ainda mais a EE. Por fim, investigamos o efeito do n'umero de antenas, em que a EE do AS sempre aumenta com o n'umero de antenas, enquanto que o SVD apresenta um n'umero 'otimo de antenas. Para o segundo cen'ario, propomos uma an'alise de EE para o esquema IDF, auxiliada por um canal de retorno para realizar a selec¸ ˜ao de rel'es. Al'em disso, comparamos o desempenho do IDF com os esquemas MIMO n˜ao-cooperativos. Os resultados mostram que uma melhor EE 'e obtida por meio de t'ecnicas de selec¸ ˜ao de antenas, principalmente quando aplicadas tanto no transmissor quanto no receptor. Tamb'em analisamos o impacto do rel'e na cooperac¸ ˜ao, uma vez que o n'o do rel'e opera apenas se necess'ario, a maior parte da carga de reconfigurabilidade 'e do rel'e, enquanto os modos de operac¸ ˜ao do PA e do LNA tendem a ser razoavelmente fixados nos n'os de origem e destino. Por fim, os resultados mostram que o n'umero de rel'es contribui para alcanc¸ar transmiss˜oes de longa distˆancia. Palavras-chave: Eficiˆencia Energ'etica, Transceptores de RF Reconfigur'aveis, Diversidade Espacial, M'ultiplas Antenas, Comunicac¸ ˜oes Cooperativas.Abstract: High energy efficiency (EE) is crucial for Internet of Things applications that operate remotely, since wireless nodes are typically battery-powered. Different spatial diversity techniques such as the use of multiple antennas (MIMO) at the transmitter and receiver nodes, as well as the use of cooperative communication can be exploited to improve the EE. In addition, the use of radio frequency (RF) transceivers are considered an interesting solution for powerrestricted systems, as they allow changing their operating point, as well as their power consumption, adapting to different communication requirements. In this thesis, a novel energy-saving approach includes in the communication system model the use of reconfigurable RF transceivers. More specifically, the components involved in our power consumption optimization framework are the power amplifier (PA) at the transmitter and the low noise amplifier (LNA) at the receiver. Our goal is to show that RF circuits based on multimode operation can significantly improve the EE. Thus, we perform a joint selection of the best operating modes for the PA and LNA circuits for different transmission schemes in two network scenarios: i) non-cooperative communication where the nodes are equipped with multiple antennas, for which we consider antenna selection (AS) and singular value decomposition (SVD) beamforming; and ii) cooperative communication where the nodes are equipped with single antenna, for which we consider incremental decode and forward (IDF) relaying. In our first proposed scenario, we compare the reconfigurable PA and LNA circuits with state-of-the-art non-reconfigurable RF amplifiers available in the literature. In this comparison, by exploiting the characteristics of reconfigurable RF amplifiers, we show an EE improvement of more than 40% at short distances for MIMO communications. When comparing MIMO schemes, the AS technique performs better for shorter distances, while the SVD allows for longer transmissions, as it exploits all available antennas. In addition, the optimization of the spectral efficiency contributes to further increase the EE. Finally, we investigate the effect of the number of antennas, in which the EE of AS always increases with the number of antennas, while SVD presents an optimal number of antennas. For the second scenario, we propose an EE analysis for the IDF scheme, aided by a feedback channel to perform relay selection. In addition, we compare the performance of the IDF with non-cooperative MIMO schemes. The results show that a better EE is obtained through antenna selection techniques, especially when applied at both transmitter and receiver. We also analyze the impact of the relay on cooperation, as the relay node operates only if necessary, most of the reconfigurability charge ends up at the relay, whereas the PA and LNA operating modes tend to be reasonably fixed at the source and destination nodes. Finally, results show that the number of relays contributes to achieving long distance transmissions. Keywords: Energy Efficiency, Reconfigurable RF Transceivers, Spatial Diversity, Multiple Antennas, Cooperative Communications

Design and application of reconfigurable circuits and systems

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A PVT tolerant voltage-controlled oscillator for automotive applications

This thesis focusses on the development of an integrated oscillator for automotive applications. The oscillator operates based on the Barkhausen criterion, which is a mathematical requirement used in electronics to predict whether a linear electronic circuit will oscillate. In this thesis, a voltage-controlled oscillator is designed for increased performance under various process, voltage and temperature (PVT) conditions. By applying a voltage reference block, the output frequency of 0.5MHz, 0.75MHz, 1MHz or 1.25MHz can be obtained. In order to compensate for the variations at PVT corners, the trimming technology is applied to increase the accuracy. The supply voltage is considered to be varying between 2.1V and 5.5V while the temperature range is -40oC -125oC.Includes bibliographical references

Osciladores de ultra-baixa-tensão com aplicação em circuitos de captação de energia

Tese (doutorado) - Universidade Federal de Santa Catarina, Centro Tecnológico, Programa de Pós-Graduação em Engenharia Elétrica, Florianópolis, 2014Abstract: This thesis describes the analysis and design of oscillators and charge pumps that can operate with very low supply voltages. The focus is on operation of the MOS transistor in the triode region owing to the limited voltage options available. Special attention has been given to the properties of the zero-VT transistor due to its high drive capability at low voltage. In order to investigate the minimum supply voltage for MOSFET oscillators, three topologies were studied. Two of them, namely the enhanced swing ring and the enhanced swing Colpitts oscillators, can operate with supply voltages below the thermal voltage, kT =q. Simplified theoretical expressions for the minimum supply voltage, oscillation frequency and minimum transistor gain of the oscillators were derived. Measurement results obtained using prototypes built with zero-VT transistors verified the operation of the oscillators for a supply voltage as low as 30 mV and 3.5 mV with high swing amplitude for arrangements built with integrated and off-theshelfinductors, respectively. The application of the ultra-low-voltage oscillators to energy harvesting circuits was addressed in this work. In order to convert the ac signal of the oscillator into a dc signal, the popular Dickson charge pump converter was employed. Expressions for the output voltage, input resistance and power converter efficiency of the Dickson charge pump operating at ultra-low voltages were derived. Experimental results obtained with prototypes built with the enhanced swing ring oscillator and the Dickson charge pump confirmed the feasibility of obtaining a dc output equal to 1 V at current consumptions of 100 nA and 1 µA from input voltages of 10 mV and 23 mV, respectively.O presente trabalho apresenta a análise, projeto e experimentação de osciladores e conversores dc-dc elevadores operando a muito baixas tensões de alimentação. Devido aos baixos valores de tensão de alimentação de interesse deste trabalho, especial atenção foi dada à operação do transistor MOS na região triodo e às propriedades do transistor zero-VT, graças a sua alta capacidade de corrente para baixas tensões. Com o objetivo de investigar a mínima tensão de alimentação de osciladores a MOSFET, três topologias foram estudadas. Duas delas, chamadas de oscilador em anel com elevada excursão desinal e oscilador Colpitts com elevada excursão de sinal, podem trabalhar com tensões de alimentação inferiores à tensão térmica, kT /q. Expressões simplificadas para a mínima tensão de alimentação, frequência de oscilação e mínimo ganho do transistor foram derivadas para cada topologia. Resultados experimentais obtidos com protótipos implementados com transistores zero-VT comprovam a operação dos osciladores com tensões tão baixas quanto 30 mV e 3,5 mV em circuitos construídos com indutores integrados e discretos, respectivamente. A aplicação dos osciladores a circuitos de captação de energia (energy harvesting circuits) a partir de fontes de alimentação de ultra-baixa-tensão foi estudada neste trabalho. Com o propósito de converter tensões ac geradas pelos osciladores em sinais dc, o clássico conversor Dickson foi utilizado. Expressões para a tensão de saída, resistência de entrada e eficiência de conversão de potência do conversor Dickson operando a ultra-baixas-tensões foram derivadas. Resultados experimentais obtidos com protótipos construídos com o oscilador em anel com elevada excursão de sinal e com o conversor Dickson, provaram a possibilidade de se obter uma tensão dc na saída de 1 V para correntes de carga de 100 nA e 1 µA a partir de tensões de entrada de 10 mV e 23 mV, respectivamente

Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration

Due to the ever-growing requirements in high performance data computation, multiprocessor systems have been proposed to solve the bottlenecks in uniprocessor systems. Developing efficient multiprocessor systems requires effective exploration of design choices like application scheduling, mapping, and architecture design. Also, fault tolerance in multiprocessors needs to be addressed. With the advent of nanometer-process technology for chip manufacturing, realization of multiprocessors on SoC (MpSoC) is an active field of research. Developing efficient low power, fault-tolerant task scheduling, and mapping techniques for MpSoCs require optimized algorithms that consider the various scenarios inherent in multiprocessor environments. Therefore there exists a need to develop a simulation framework to explore and evaluate new algorithms on multiprocessor systems. This work proposes a modular framework for the exploration and evaluation of various design algorithms for MpSoC system. This work also proposes new multiprocessor task scheduling and mapping algorithms for MpSoCs. These algorithms are evaluated using the developed simulation framework. The paper also proposes a dynamic fault-tolerant (FT) scheduling and mapping algorithm for robust application processing. The proposed algorithms consider optimizing the power as one of the design constraints. The framework for a heterogeneous multiprocessor simulation was developed using SystemC/C++ language. Various design variations were implemented and evaluated using standard task graphs. Performance evaluation metrics are evaluated and discussed for various design scenarios