Data driven optimization in SAR ADC

Recent publications show that successive approximation register (SAR) analog to digital converters (ADC) are capable of achieving high efficiency over other ADC topologies. Furthermore, techniques have been adopted to process signals with low activity periods, such as biomedical and industrial sensors. Prior work used least- significant bit first quantization (LSBFQ) to conserve capacitor switching energy and comparator decisions (bitcycles). This work improves on the published least significant bit (LSB) first successive approximation ADC by restructuring its algorithm for further energy efficient switching, lowering its bitcycle range, and extending its range of applications. For target applications, these proposed solutions will outperform the bit-skipping LS­BFQ and the merged capacitor switching (MCS) SAR, the most energy-efficient traditional most significant bit (MSB) first SAR.Keywords: Adaptive SAR, ADC, LSB-First, LSB First, LSBFQ, SAR, ASB, SSB, Successive Approximation Algorith

The development of a power spectral density processor for C and L band airborne radar scatterometer sensor systems

A real-time signal processor was developed for the NASA/JSC L-and C-band airborne radar scatterometer sensor systems. The purpose of the effort was to reduce ground data processing costs. Conversion of two quadrature channels of data (like and cross polarized) was made to obtain Power Spectral Density (PSD) values. A chirp-z transform (CZT) approach was used to filter the Doppler return signal and improved high frequency and angular resolution was realized. The processors have been tested with record signals and excellent results were obtained. CZT filtering can be readily applied to scatterometers operating at other wavelengths by altering the sample frequency. The design of the hardware and software and the results of the performance tests are described in detail

SFERA: An Integrated Circuit for the Readout of X and γ-Ray Detectors

In this work we present SFERA, a low-noise fully-programmable 16 channel readout ASIC designed for both X- and γ-ray spectroscopy and imaging applications. The chip is designed to process signals coming from solid-state detectors and CMOS preamplifiers. The design has been guided by the use of Silicon Drift Detectors (SDDs) and CUBE charge sensitive amplifiers (CSAs), although we consider the ASIC sufficiently versatile to be used with other types of detectors. Five different gains are implemented, namely 2800 e-, 4400 e-, 10000 e-, 14000 e- and 20000 e-, considering the input connected to a 25 fF feedback capacitance CMOS preamplifier. Filter peaking times (tP) are also programmable among 0.5, 1, 2, 3, 4 and 6 μs. Each readout channel is the cascade of a 9th order semi-Gaussian shaping-amplifier (SA) and a peak detector (PKS), followed by a dedicated pile-up rejection (PUR) digital logic. Three data multiplexing strategies are implemented: the so-called polling X, intended for high-rate X-ray applications, the polling γ, for scintillation light detection and the sparse, for signals derandomization. The spectroscopic characterization has shown an energy resolution of 122.1 eV FWHM on the Mn-Kα line of an 55Fe X-ray source using a 10 mm2 SDD cooled at -35 °C at 4 μs filter peaking time. The measured resolution is 130 eV at the peaking time of 500 ns. At 1 Mcps input count rate and 500 ns peaking time, we have measured 42% of processed events at the output of the ASIC after the PUR selection. Output data can be digitized on-chip by means of an embedded 12-bit successive-approximation ADC. The effective resolution of the data converter is 10.75-bit when operated at 4.5 MS/s. The chosen technology is the AMS 0.35 μm CMOS and the chip area occupancy is 5× 5 mm2

Programmable-System-on-Chip-based data acquisition system for educational purposes

The project aims to implement a PSoC DVK based DAS system learning resource. The idea is to provide a way to develop signal acquiring basic knowledge, as well as a tool to implement simple measures. In order to do it, hardware and software have been implemented. Hardware consists of PSoC DVK, which has the functions of AC and DC signal acquiring and generating, showing information about the selected function and the acquired signal through a display, and transmitting the acquired samples through the RS-232 communication. Software allows PSoC interacting and showing the acquired samples over the time and in a histogram. The system provides the capability for selecting the ADC type between an integrating, a SAR and a dual integrating. Also, different resolutions and sample rates can be selected. This allows having several configurations in order to study some signal acquiring features, such as the interference rejection capability of the integrating ADC compared to the SAR and the analog circuit response, or to study each ADC type signal acquiring. Finally, the system allows selecting the number of samples to be acquired between some preset quantities. It allows showing a detailed temporal representation of the samples acquired. Also, the input can be scaled in order to profit the ADC resolution for small amplitude signals

Real-time computer data system for the 40- by 80-foot wind tunnel facility at Ames Research Center

The background material and operational concepts of a computer-based system for an operating wind tunnel are described. An on-line real-time computer system was installed in a wind tunnel facility to gather static and dynamic data. The computer system monitored aerodynamic forces and moments of periodic and quasi-periodic functions, and displayed and plotted computed results in real time. The total system is comprised of several off-the-shelf, interconnected subsystems that are linked to a large data processing center. The system includes a central processor unit with 32,000 24-bit words of core memory, a number of standard peripherals, and several special processors; namely, a dynamic analysis subsystem, a 256-channel PCM-data subsystem and ground station, a 60-channel high-speed data acquisition subsystem, a communication link, and static force and pressure subsystems. The role of the test engineer as a vital link in the system is also described

Estación meteorológica inalámbrica, de muy bajo consumo e inteligencia embebida

El trabajo aborda la realización de una estación meteorológica alimentada mediante una placa solar. La placa emisora cuenta con una serie de sensores que dan información a cerca de la temperatura, la humedad, la presión y la iluminación. Los datos son recibidos y se implementan algoritmos de predicción del tiempo cuyo resultado es visualizado por el usuario. Uno de los objetivos fundamentales es que el sistema resultante sea de muy bajo consumo para que pueda operar durante largos períodos

New technologies for radiation-hardening analog to digital converters

Surveys of available Analog to Digital Converters (ADC) suitable for precision applications showed that none have the proper combination of accuracy and radiation hardness to meet space and/or strategic weapon requirements. A development program which will result in an ADC device which will serve a number of space and strategic applications. Emphasis was placed on approaches that could be integrated onto a single chip within three to five years

Advanced measurement systems based on digital processing techniques for superconducting LHC magnets

The Large Hadron Collider (LHC), a particle accelerator aimed at exploring deeper into matter than ever before, is currently being constructed at CERN. Beam optics of the LHC, requires stringent control of the field quality of about 8400 superconducting magnets, including 1232 main dipoles and 360 main quadrupoles to assure the correct machine operation. The measurement challenges are various: accuracy on the field strength measurement up to 50 ppm, harmonics in the ppm range, measurement equipment robustness, low measurement times to characterize fast field phenomena. New magnetic measurement systems, principally based on analog solutions, have been developed at CERN to achieve these goals. This work proposes the introduction of digital technologies to improve measurement performance of three systems, aimed at different measurement target and characterized by different accuracy levels. The high accuracy measurement systems, based on rotating coils, exhibit high performance in static magnetic field. With varying magnetic field the system accuracy gets worse, independently from coil speed, due to the limited resolution of the digital integrator currently used, and the restrictions of the standard analysis. A new integrator based on ADC conversion and numerical integration is proposed. The experimental concept validation by emulating the proposed approach on a PXI platform is detailed along with the improvements with respect to the old integrators. Two new analysis algorithms to reduce the errors in dynamic measurements are presented. The first combines quadrature detection and short time Fourier transform (STFT) of the acquired magnetic flux samples; the second approach is based on the extrapolation of the magnetic flux samples. Unlike other algorithms presented in the literature, both the proposals do not require the information about the magnet current and are able to work in real time so, can be easily implemented in firmware on DSP. The performance of the new proposals are assessed in simulation. As far as medium accuracy systems are concerned, at CERN was originally developed a probe to measure the sextupolar and decapolar field harmonics of the superconducting dipoles using a suitable Hall plates arrangement for the bucking of the main dipolar field, which is, 4 orders of magnitude higher than the measurement target. The output signals of each Hall plate belonging to the same measurement ring are mixed using analog cards. The resultant signal is proportional to the field harmonic to measure. A complete metrological characterization of this sensor was carried out, showing the limitation of a fully analog solution. The main problems found were the instability of the analog compensation cards and the impossibility to correct the non linearity effects beyond the first order. An automatic calibration procedure implemented in the new instrument software is presented to guarantee measurement repeatability. In alternative a digital bucking solution, namely the compensation of the main field after the sampling of each hall plate signal by means of numerical sum, is proposed. An implementation of this approach, based on 18 bit ADC converter, over-sampling and dithering techniques as well as compensation of the Hall plates non linearity in real time is analyzed. Finally, as far as the low accuracy measurement systems are concerned, the design of an instrument based on a rotating Hall plate to check the polarity of all LHC magnets is presented. Even if this architecture is characterized by low accuracy in the measurement of field strength and phase, the results are sufficient to identify main harmonic order, type and polarity with practically no errors, thanks to an accurate definition of the measurement algorithm. A complete metrological characterization of the prototype developed and a correction of all the systematic measurement errors was carried out. This instrument, integrated in a test bench developed ad hoc, is become the standard at CERN for the polarity test of all the magnets will compose the machine

Circuit Design for Realization of a 16 bit 1MS/s Successive Approximation Register Analog-to-Digital Converter

As the use of digital systems continues to grow, there is an increasing need to convert analog information into the digital domain. Successive Approximation Register (SAR) analog-to-digital converters are used extensively in this regard due to their high resolution, small die area, and moderate conversion speeds. However, capacitor mismatch within the SAR converter is a limiting factor in its accuracy and resolution. Without some form of calibration, a SAR converter can only reasonably achieve an accuracy of 10 bits. The Split-ADC technique is a digital, deterministic, background self-calibration algorithm that can be applied to the SAR converter. This thesis describes the circuit design and physical implementation of a novel 16-bit 1MS/s SAR analog-to-digital converter for use with the Split-ADC calibration algorithm. The system was designed using the Jazz 0.18um CMOS process, successfully operates at 1MS/s, and consumes a die area of 1.2mm2. The calibration algorithm was applied, showing an improvement in the overall accuracy of the converter

Quadrature synchronous sampling for electrical impedance plethysmography implemented on an MSP432 microcontroller

The developed project allows getting IPG through Quadrature Synchronous Sampling using the new 32 bit MCU MSP432 from texas instruments. It is able to work from ranged frequencies 10 kHz to 1 MHz with a precision of 14 bits and 10 bits respectively