52 research outputs found

    Improved physical models for advanced silicon device processing

    Get PDF
    Producción CientíficaWe review atomistic modeling approaches for issues related to ion implantation and annealing in advanced device processing. We describe how models have been upgraded to capture physical mechanisms in more detail as a response to the accuracy demanded in modern process and device modeling. Implantation and damage models based on the binary collision approximation have been improved to describe the direct formation of amorphous pockets for heavy or molecular ions. The use of amorphizing implants followed by solid phase epitaxial regrowth has motivated the development of detailed models that account for amorphization and recrystallization, considering the influence of crystal orientation and stress conditions. We apply simulations to describe the role of implant parameters to minimize residual damage, and we address doping issues that arise in non-planar structures such as FinFETs.Ministerio de Ciencia e Innovación - FEDER (Proyect TEC2014-60694-P)Junta de Castilla y León (programa de apoyo a proyectos de investigación – Ref. VA331U14

    FiliĂšre technologique hybride InGaAs/SiGe pour applications CMOS

    Get PDF
    High-mobility channel materials such as indium-galium-arsenide (InGaAs) and silicon-germanium(SiGe) alloys are considered to be the leading candidates for replacing silicon (Si) in future lowpower complementary metal-oxide-semiconductor (CMOS) circuits. Numerous challenges haveto be tackled in order to turn the high-mobility CMOS concept into an industrial solution. Thisthesis addresses the majors challenges which are the integration of InGaAs on Si, the formationof high-quality gate stacks and self-aligned source and drain (S/D) regions, the optimizationof self-aligned transistors and the co-integration of InGaAs and SiGe into CMOS circuits. Allinvestigated possible solutions are proposed in the framework of very-large-scale integration requirements.Chapter 2 describes two different methods to integrate InGaAs on Si. Chapter 3 detailsthe developments of key process modules for the fabrication of self-aligned InGaAs metal-oxidesemiconductorfield-effect transistors (MOSFETs). Chapter 4 covers the realization of varioustypes of self-aligned MOSFETs towards the improvement of their performance. Finally, chapter5 demonstrates three different methods to make hybrid InGaAs/SiGe CMOS circuits.Les materiaux Ă  forte mobilitĂ© comme l’InGaAs et le SiGe sont considĂ©rĂ©s comme des candidats potentiels pour remplacer le Si dans les circuits CMOS futurs. De nombreux dĂ©fis doivent ĂȘtre surmontĂ©s pour transformer ce concept en rĂ©alitĂ© industrielle. Cette thĂšse couvre les principaux challenges que sont l’intĂ©gration de l’InGaAs sur Si, la formation d’oxydes de grille de qualitĂ©, la rĂ©alisation de rĂ©gions source/drain auto-alignĂ©es de faible rĂ©sistance, l’architecture des transistors ou encore la co-intĂ©gration de ces matĂ©riaux dans un procĂ©dĂ© de fabrication CMOS.Les solutions envisagĂ©es sont proposĂ©es en gardant comme ligne directrice l’applicabilitĂ© des mĂ©thodes pour une production de grande envergure.Le chapitre 2 aborde l’intĂ©gration d’InGaAs sur Si par deux mĂ©thodes diffĂ©rentes. Le chapitre3 dĂ©taille le dĂ©veloppement de modules spĂ©cifiques Ă  la fabrication de transistors auto-alignĂ©s sur InGaAs. Le chapitre 4 couvre la rĂ©alisation de diffĂ©rents types de transistors auto-alignĂ©s sur InGaAs dans le but d’amĂ©liorer leurs performances. Enfin, le chapitre 5 prĂ©sente trois mĂ©thodes diffĂ©rentes pour rĂ©aliser des circuits hybrides CMOS Ă  base d’InGaAs et de SiGe

    Self-aligned gallium arsenide heterojunction bipolar transistor using refractory metallisation

    Get PDF
    Improvements in epitaxial growth and processing technologies have revived a great deal of interest in the heterojunction bipolar transistor (HBT). In this project, AIGaAs/GaAS HBTs have been fabricated using a new self-aligned process which exploits the characteristics of some refractory metals deposited by sputtering to obtain a T-shaped contact structure for the emitter. wet and dry etching techniques were used to fabricate the T-shaped contact. A refractory metallisation system consisting of sequentially sputtered layers of Ge/Mo/Ni was investigated for contacting the emitter of the transistor. After alloying in a thermal furnace at 750°C for 30 minutes in a nitrogen atmOSPhere, a low specific contact resistance of 2 x 10-6 ohm-cm was measured by standard transmission line model (TLM) for measurement of contact resistance. A metallisation system consisting of sequentially evaporated AU/Zn/Au was used for the base and Ni/AuGe/Ni/AU was used for the collector. Alloying with the same condition1 as above gave specific contact re1istances of 1.2 x 10-6 ohm-cm for the base and 8.6 x 10 -6 ohm-cm for the collector. AS an alternative to ion implantation, zinc diffusion was used as an alternative technique to dope the base contact region. The acceptor concentration profile of the diffused region was studied by 'Hall and Stripe' technique and a surface concentration of 1 x 10 20 cm -3 was measured. This highly doped base contact region can be used to achieve low ohmic contact to the base. Results show that for devices designed with similar dimensions for both processes, the new self-aligned process shows a net improvement in the frequency response of the devices (ft= 10.7GHZ and &nax=9.8GHZ for self-aligned and ft=8.0GHZ and for conventional 8um HBT)

    Journal of Telecommunications and Information Technology, 2009, nr 4

    Get PDF
    kwartalni

    Strain engineering of Ge/GeSn photonic structures

    Get PDF
    Silicon compatible light sources have been referred to as the \holy grail" for Si photonics. Such devices would give the potential for a range of applications; from optical interconnects on integrated circuits, to cheap optical gas sensing and spectroscopic devices on a Si platform. Whilst numerous heterogeneous integration schemes for integrating III-V lasers with Si wafers are being pursued, it would be far easier and cheaper to use the epitaxial tools already in complementary-metal-oxide-semiconductor (CMOS) lines, where Ge and SiGe chemical vapour deposition is used in a number of advanced technology nodes. Germanium is an efficient absorber, but a poor emitter due to a band-structure which is narrowly indirect, but by only 140 meV. Through the application of strain, or by alloying with Sn, the Ge bandstructure can be engineered to become direct bandgap, making it an effcient light emitter. In this work, silicon nitride stressor technologies, and CMOS compatible processes are used to produce levels of tensile strain in Ge optical micro-cavities where a transition to direct bandgap is predicted. The strain distribution, and the optical emission of a range of Ge optical cavities are analyzed, with an emphasis on the effect of strain distribution on the material band-structure. Peak levels of strain are reported which are higher than that reported in the literature using comparable techniques. Furthermore, these techniques are applied to GeSn epi-layers and demonstrate that highly compressive GeSn alloys grown pseudomorphically on Ge virtual substrates, can be transformed to direct bandgap materials, with emission >3 m wavelength { the longest wavelength emission demonstrated from GeSn alloys. Such emission is modeled to have a good overlap with methane absorption lines, indicating that there is huge potential for the such technologies to be used for low cost, Si compatible gas sensing in the mid-infrared

    Strain integration and performance optimization in sub-20nm FDSOI CMOS technology

    Get PDF
    La technologie CMOS Ă  base de Silicium complĂštement dĂ©sertĂ© sur isolant (FDSOI) est considĂ©rĂ©e comme une option privilĂ©giĂ©e pour les applications Ă  faible consommation telles que les applications mobiles ou les objets connectĂ©s. Elle doit cela Ă  son architecture garantissant un excellent comportement Ă©lectrostatique des transistors ainsi qu'Ă  l'intĂ©gration de canaux contraints amĂ©liorant la mobilitĂ© des porteurs. Ce travail de thĂšse explore des solutions innovantes en FDSOI pour nƓuds 20nm et en deçà, comprenant l'ingĂ©nierie de la contrainte mĂ©canique Ă  travers des Ă©tudes sur les matĂ©riaux, les dispositifs, les procĂ©dĂ©s d'intĂ©gration et les dessins des circuits. Des simulations mĂ©caniques, caractĂ©risations physiques (”Raman), et intĂ©grations expĂ©rimentales de canaux contraints (sSOI, SiGe) ou de procĂ©dĂ©s gĂ©nĂ©rant de la contrainte (nitrure, fluage de l'oxyde enterrĂ©) nous permettent d'apporter des recommandations pour la technologie et le dessin physique des transistors en FDSOI. Dans ce travail de thĂšse, nous avons Ă©tudiĂ© le transport dans les dispositifs Ă  canal court, ce qui nous a amenĂ© Ă  proposer une mĂ©thode originale pour extraire simultanĂ©ment la mobilitĂ© des porteurs et la rĂ©sistance d'accĂšs. Nous mettons ainsi en Ă©vidence la sensibilitĂ© de la rĂ©sistance d'accĂšs Ă  la contrainte que ce soit pour des transistors FDSOI ou nanofils. Nous mettons en Ă©vidence et modĂ©lisons la relaxation de la contrainte dans le SiGe apparaissant lors de la gravure des motifs et causant des effets gĂ©omĂ©triques (LLE) dans les technologies FDSOI avancĂ©es. Nous proposons des solutions de type dessin ainsi que des solutions technologiques afin d'amĂ©liorer la performance des cellules standard digitales et de mĂ©moire vive statique (SRAM). En particulier, nous dĂ©montrons l'efficacitĂ© d'une isolation duale pour la gestion de la contrainte et l'extension de la capacitĂ© de polarisation arriĂšre, qui un atout majeur de la technologie FDSOI. Enfin, la technologie 3D sĂ©quentielle rend possible la polarisation arriĂšre en rĂ©gime dynamique, Ă  travers une co-optimisation dessin/technologie (DTCO).The Ultra-Thin Body and Buried oxide Fully Depleted Silicon On Insulator (UTBB FDSOI) CMOS technology has been demonstrated to be highly efficient for low power and low leakage applications such as mobile, internet of things or wearable. This is mainly due to the excellent electrostatics in the transistor and the successful integration of strained channel as a carrier mobility booster. This work explores scaling solutions of FDSOI for sub-20nm nodes, including innovative strain engineering, relying on material, device, process integration and circuit design layout studies. Thanks to mechanical simulations, physical characterizations and experimental integration of strained channels (sSOI, SiGe) and local stressors (nitride, oxide creeping, SiGe source/drain) into FDSOI CMOS transistors, we provide guidelines for technology and physical circuit design. In this PhD, we have in-depth studied the carrier transport in short devices, leading us to propose an original method to extract simultaneously the carrier mobility and the access resistance and to clearly evidence and extract the strain sensitivity of the access resistance, not only in FDSOI but also in strained nanowire transistors. Most of all, we evidence and model the patterning-induced SiGe strain relaxation, which is responsible for electrical Local Layout Effects (LLE) in advanced FDSOI transistors. Taking into account these geometrical effects observed at the nano-scale, we propose design and technology solutions to enhance Static Random Access Memory (SRAM) and digital standard cells performance and especially an original dual active isolation integration. Such a solution is not only stress-friendly but can also extend the powerful back-bias capability, which is a key differentiating feature of FDSOI. Eventually the 3D monolithic integration can also leverage planar Fully-Depleted devices by enabling dynamic back-bias owing to a Design/Technology Co-Optimization

    Etude des transistors MOSFET Ă  barriĂšre Schottky, Ă  canal Silicium et Germanium sur couches minces

    Get PDF
    Until the early 2000’s Dennard’s scaling rules at the transistor level have enabled to achieve a performance gain while still preserving the basic structure of the MOSFET building block from one generation to the next. However, this conservative approach has already reached its limits as shown by the introduction of channel stressors for the sub-130 nm technological nodes, and later high-k/metal gate stacks for the sub-65 nm nodes. Despite the introduction of high-k gate dielectrics, constraints in terms of gate leakage and reliability have been delaying the diminution of the equivalent oxide thickness (EOT). Concurrently, lowering the supply voltage (VDD) has become a critical necessity to reduce both the active and passive power density in integrated circuits. Hence the challenge: how to keep decreasing both gate length and supply voltage faster than the EOT without losing in terms of ON-state/OFF-state performance trade-off? Several solutions can be proposed aiming at solving this conundrum for nanoscale transistors, with architectures in rupture with the plain old Silicon-based MOSFET with doped Source and Drain invented in 1960. One approach consists in achieving an ION increase while keeping IOFF (and Vth) mostly unchanged. Specifically, two options are considered in detail in this manuscript through a review of their respective historical motivations, state-of-the-art results as well as remaining fundamental (and technological) challenges: i/ the reduction of the extrinsic parasitic resistance through the implementation of metallic Source and Drain (Schottky Barrier FET architecture); ii/ the reduction of the intrinsic channel resistance through the implementation of Germanium-based mobility boosters (Ge CMOS, compressively-strained SiGe channels, n-sSi/p-sSiGe Dual Channel co-integration). In particular, we study the case of thin films on insulator (SOI, SiGeOI, GeOI substrates), a choice justified by: the preservation of the electrostatic integrity for the targeted sub-22nm nodes; the limitation of ambipolar leakage in SBFETs; the limitation of junction leakage in (low-bandgap) Ge-based FETs. Finally, we show why, and under which conditions the association of the SBFET architecture with a Ge-based channel could be potentially advantageous with respect to conventional Si CMOS.Jusqu’au dĂ©but des annĂ©es 2000, les rĂšgles de scaling de Dennard ont permis de rĂ©aliser des gains en performance tout en conservant la structure de la brique de base transistor d’une gĂ©nĂ©ration technologique Ă  la suivante. Cependant, cette approche conservatrice a d’ores et dĂ©jĂ  atteint ses limites, comme en tĂ©moigne l’introduction de la contrainte mĂ©canique pour les gĂ©nĂ©rations sub-130nm, et les empilements de grille mĂ©tal/high-k pour les nƓuds sub-65nm. MalgrĂ© l’introduction de diĂ©lectriques Ă  forte permittivitĂ©, des limites en termes de courants de fuite de grille et de fiabilitĂ© ont ralenti la diminution de l’épaisseur Ă©quivalente d’oxyde (EOT). De façon concommitante, la diminution de la tension d’alimentation (VDD) est devenue une prioritĂ© afin de rĂ©duire la densitĂ© de puissance dissipĂ©e dans les circuits intĂ©grĂ©s. D’oĂč le dĂ©fi actuel: comment continuer de rĂ©duire Ă  la fois la longueur de grille et la tension d’alimentation plus rapidement que l’EOT sans pour autant dĂ©grader le rapport de performances aux Ă©tats passant et bloquĂ© (ON et OFF) ? Diverses solutions peuvent ĂȘtre proposĂ©es, passant par des architectures s’éloignant du MOSFET conventionnel Ă  canal Si avec source et drain dopĂ©s tel que dĂ©fini en 1960. Une approche consiste en rĂ©aliser une augmentation du courant passant (ION) tout en laissant le courant Ă  l’état bloquĂ© (IOFF) et la tension de seuil (Vth) inchangĂ©s. ConcrĂštement, deux options sont considĂ©rĂ©es en dĂ©tail dans ce manuscrit Ă  travers une revue de leurs motivations historiques respectives, les rĂ©sultats de l’état de l’art ainsi que les obstacles (fondamentaux et technologiques) Ă  leur mise en Ɠuvre : i/ la rĂ©duction de la rĂ©sistance parasite extrinsĂšque par l’introduction de source et drain mĂ©talliques (architecture transistor Ă  barriĂšre Schottky) ; ii/ la rĂ©duction de la rĂ©sistance de canal intrinsĂšque par l’introduction de matĂ©riaux Ă  haute mobilitĂ© Ă  base de Germanium (CMOS Ge, canaux SiGe en contrainte compressive, co-intĂ©gration Dual Channel n-sSi/p-sSiGe). En particulier, nous Ă©tudions le cas de couches minces sur isolant (substrats SOI, SiGeOI, GeOI), un choix motivĂ© par: la prĂ©servation de l’intĂ©gritĂ© Ă©lectrostatique pour les nƓuds technologiques sub-22nm; la limitation du courant de fuite ambipolaire dans les SBFETs; la limitation du courant de fuites de jonctions dans les MOSFETs Ă  base de Ge (qui est un matĂ©riau Ă  faible bandgap). Enfin, nous montrons pourquoi et dans quelles conditions l’association d’une architecture SBFET et d’un canal Ă  base de Germanium peut ĂȘtre avantageuse vis-Ă -vis du CMOS Silicium conventionnel

    Feature Papers in Electronic Materials Section

    Get PDF
    This book entitled "Feature Papers in Electronic Materials Section" is a collection of selected papers recently published on the journal Materials, focusing on the latest advances in electronic materials and devices in different fields (e.g., power- and high-frequency electronics, optoelectronic devices, detectors, etc.). In the first part of the book, many articles are dedicated to wide band gap semiconductors (e.g., SiC, GaN, Ga2O3, diamond), focusing on the current relevant materials and devices technology issues. The second part of the book is a miscellaneous of other electronics materials for various applications, including two-dimensional materials for optoelectronic and high-frequency devices. Finally, some recent advances in materials and flexible sensors for bioelectronics and medical applications are presented at the end of the book
    • 

    corecore