FPGA Implementation of Floating Point Reciprocator Using Binomial Expansion Method

Floating-point support has become a mandatory feature of new micro processors due to the prevalence of business, technical, and recreational applications that use these operations.  In these operations Floating-point division is generally regarded as a low frequency, high latency operation in typical floating-point applications. So due to this not much development had taken place in this field. But nowadays floating point divider has become indispensable and increasingly important in many scientific and signal processing applications.In this paper we implement floating point reciprocator for both single precision and double precision floating point numbers using FPGA. Here the implementation is based on the binomial expansion method. By comparing with previous works the modules occupy less area with a higher performance and less latency. The designs trade off either 1 unit in last-place (ulp) or 2 ulp of accuracy (for double or single precision respectively), without rounding, to obtain a better implementation

Adaptive FPGA NoC-based Architecture for Multispectral Image Correlation

An adaptive FPGA architecture based on the NoC (Network-on-Chip) approach is used for the multispectral image correlation. This architecture must contain several distance algorithms depending on the characteristics of spectral images and the precision of the authentication. The analysis of distance algorithms is required which bases on the algorithmic complexity, result precision, execution time and the adaptability of the implementation. This paper presents the comparison of these distance computation algorithms on one spectral database. The result of a RGB algorithm implementation was discussed

Fast Compensated Algorithms for the Reciprocal Square Root, the Reciprocal Hypotenuse, and Givens Rotations

The reciprocal square root is an important computation for which many very sophisticated algorithms exist (see for example \cite{863046,863031} and the references therein). In this paper we develop a simple differential compensation (much like those developed in \cite{borges}) that can be used to improve the accuracy of a naive calculation. The approach relies on the use of the fused multiply-add (FMA) which is widely available in hardware on a variety of modern computer architectures. We then demonstrate how to combine this approach with a somewhat inaccurate but fast square root free method for estimating the reciprocal square root to get a method that is both fast (in computing environments with a slow square root) and, experimentally, highly accurate. Finally, we show how this same approach can be extended to the reciprocal hypotenuse calculation and, most importantly, to the construction of Givens rotations

Calculation Methodology for Flexible Arithmetic Processing

Paper submitted to the IFIP International Conference on Very Large Scale Integration (VLSI-SOC), Darmstadt, Germany, 2003.A new operation model of flexible calculation that allows us to adjust the operation delay depending on the available time is presented. The operation method design uses look-up tables and progressive construction of the result. The increase in the operators’ granularity opens up new possibilities in calculation methods and microprocessor design. This methodology, together with the advances in technology, enables the functions of an arithmetic unit to be implemented on the basis of techniques based on stored data that provide quality results and systematization in the implementation. The proposed techniques are applied in the design of a multiplier operator. We report an evaluation of the architecture in area, delay and computation error, as well as a suitable implementation of an application example in FPGA to validate the design.This work is being backed by grant DPI2002-04434-C04-01 from the Ministerio de Ciencia y Tecnología of the Spanish Government

Partial Product Reduction based on Look-Up Tables

In this paper a new technique for partial product reduction based on the use of look-up tables for efficient processing is presented. We describe how to construct counter devices with pre-calculated data and their subsequent integration into the whole operation. The development of reduction trees organizations for this kind of devices uses the inherent integration benefits of computer memories and offers an alternative implementation to classic operation methods. Therefore, in our experiments we compare our implementation model with CMOS technology model in homogeneous terms

Time-Precision Flexible Arithmetic Unit

Paper submitted to the XVIII Conference on Design of Circuits and Integrated Systems (DCIS), Ciudad Real, España, 2003.A new conception of flexible calculation that allows us to adjust an operation depending on the available time computation is presented. The proposed arithmetic unit is based on this principle. It contains a control operation module that determines the process time of each calculation. The operation method design uses precalculated data stored in look-up tables, which provide, above all, quality results and systematization in the implementation of low level primitives that set parameters for the processing time. We report an evaluation of the architecture in area, delay and computation error, as well as a suitable implementation in FPGA to validate the design.This work is being backed by grant DPI2002-04434-C04-01 from the Ministerio de Ciencia y Tecnología of the Spanish Government

Time-Precision Flexible Adder

Paper submitted to 10th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Sharjah, Emiratos Árabes, 2003.A new conception of flexible calculation that allows us to adjust a sum depending on the available time computation is presented. More specifically, the objective is to obtain a calculation model that makes the processing time/precision more flexible. The addition method is based on carry-select scheme adder and the proposed design uses precalculated data stored in look-up tables, which provide, above all, quality results and systematization in the implementation of low level primitives that set parameters for the processing time. We report an evaluation of the architecture in area, delay and computation error, as well as a suitable implementation in FPGA to validate the design.This work is being backed by grant DPI2002-04434-C04-01 from the Ministerio de Ciencia y Tecnología of the Spanish Government

Table-Free Seed Generation for Hardware Newton–Raphson Square Root and Inverse Square Root Implementations in IoT Devices

Consejeríaa de Economía y Conocimiento de la Junta de Andalucía y el Fondo Europeo de Desarrollo Regional (FEDER) bajo el proyecto B-TIC-588-UGR2