VCO start-up and stability analysis using time varying root locus

The oscillator circuit is one of the key components of the communication systems. It is necessary for an oscillator to provide the proper oscillations in order to confirm the stable operation of a communication circuit. There are many different analysis methods of analyzing the start-up and frequency stability of a system, but mostly it fails to analyze properly due to the parasitics involved. Somehow if any of them manages to compute the analysis it would be very complex, difficult and time consuming. The time varying root locus (TVRL) approach can be utilized to analyze the start-up and frequency behavior of different oscillator designs. It is a theoretical based technique that can provide further insights into a circuit designer for oscillator operation. To analyze the start-up behavior, a semi-symbolic TVRL approach can be used with the help of the numerical QZ (Generalized Schur Decomposition) algorithm. By finding the time varying roots of polynomials, TVRL can help to estimate the undesired operating points. A symbolic TVRL analysis is capable of computing the system roots during an oscillation with the help of Muller algorithm. Different numerical and the CAD (Computer Aided Design) tool are involved to implement this theoretical approach. Cadence 45nm CMOS General Process Design Kit (GPDK) helps to design the required schematic and SpectreRF simulator computes the time varying periodic solutions. Maple script can form an admittance matrix which is later used in MATALB to compute the final TVRL trajectories of dominant poles. The corresponding results are then analyzed to detect the failure mechanism which is responsible for relaxation oscillations. In this thesis, an active inductor quadrature voltage controlled oscillator and five stage ring oscillator circuits are proposed to analyze thoroughly with the help of TVRL approach. The above mentioned techniques along with some extra computations have been implemented to verify whether the proposed circuits can overcome the relaxation oscillations and can produce the proper sinusoidal waveforms or there is a need to devise some modifications

Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort

Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort

Analysis and design of sinusoidal quadrature RC-oscillators

Modern telecommunication equipment requires components that operate in many different frequency bands and support multiple communication standards, to cope with the growing demand for higher data rate. Also, a growing number of standards are adopting the use of spectrum efficient digital modulations, such as quadrature amplitude modulation (QAM) and orthogonal frequency division multiplexing (OFDM). These modulation schemes require accurate quadrature oscillators, which makes the quadrature oscillator a key block in modern radio frequency (RF) transceivers. The wide tuning range characteristics of inductorless quadrature oscillators make them natural candidates, despite their higher phase noise, in comparison with LC-oscillators. This thesis presents a detailed study of inductorless sinusoidal quadrature oscillators. Three quadrature oscillators are investigated: the active coupling RC-oscillator, the novel capacitive coupling RCoscillator, and the two-integrator oscillator. The thesis includes a detailed analysis of the Van der Pol oscillator (VDPO). This is used as a base model oscillator for the analysis of the coupled oscillators. Hence, the three oscillators are approximated by the VDPO. From the nonlinear Van der Pol equations, the oscillators’ key parameters are obtained. It is analysed first the case without component mismatches and then the case with mismatches. The research is focused on determining the impact of the components’ mismatches on the oscillator key parameters: frequency, amplitude-, and quadrature-errors. Furthermore, the minimization of the errors by adjusting the circuit parameters is addressed. A novel quadrature RC-oscillator using capacitive coupling is proposed. The advantages of using the capacitive coupling are that it is noiseless, requires a small area, and has low power dissipation. The equations of the oscillation amplitude, frequency, quadrature-error, and amplitude mismatch are derived. The theoretical results are confirmed by simulation and by measurement of two prototypes fabricated in 130 nm standard complementary metal-oxide-semiconductor (CMOS) technology. The measurements reveal that the power increase due to the coupling is marginal, leading to a figure-of-merit of -154.8 dBc/Hz. These results are consistent with the noiseless feature of this coupling and are comparable to those of the best state-of-the-art RC-oscillators, in the GHz range, but with the lowest power consumption (about 9 mW). The results for the three oscillators show that the amplitude- and the quadrature-errors are proportional to the component mismatches and inversely proportional to the coupling strength. Thus, increasing the coupling strength decreases both the amplitude- and quadrature-errors. With proper coupling strength, a quadrature error below 1° and amplitude imbalance below 1% are obtained. Furthermore, the simulations show that increasing the coupling strength reduces the phase noise. Hence, there is no trade-off between phase noise and quadrature error. In the twointegrator oscillator study, it was found that the quadrature error can be eliminated by adjusting the transconductances to compensate the capacitance mismatch. However, to obtain outputs in perfect quadrature one must allow some amplitude error

Ultra-low power, low-voltage transmitter at ISM band for short range transceivers

Tezin basılısı İstanbul Şehir Üniversitesi Kütüphanesi'ndedir.The increasing demand for technology to be used in every aspect of our lives has led the way to many new applications and communication standards. WSN and BAN are some of the new examples that utilize electronic circuit design in the form of very small sensors to perform their applications. They consist of small sensor nodes and have applications ranging from entertainment to medicine. Requirements such as decreasing the area and the power consumption help to have longer-lasting batteries and smaller devices. The standard paves the way for the devices from different vendors to communicate with each other, and that motivates us to make designs as compatible with the standard as it can be. In this thesis, an ultra-low power high efficient transmitter with a small area working at 2.4 GHz have been designed for BAN applications. A study on the system-view perspective is important in optimizing the area and power since the transmitter architecture can change the circuit design. From a circuit design perspective, seeking to decrease power consumption means thinking of new techniques to implement the same function or a new system. Inspired by new trends, this research presents a design solution to the previously mentioned problem and hopefully, after fabrication, the measured results will match the simulated results to prove the validity of the design.Declaration of Authorship ii Abstract iv Öz v Acknowledgments vii List of Figures x List of Tables xiii Abbreviations xiv 1 Introduction 1 1.1 Background and Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Communication Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2.1 Digital Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2.2 Unwanted Power Limitations . . . . . . . . . . . . . . . . . . . . . 3 1.2.3 Multiple Access Techniques . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Transmitter System Level Specifications . . . . . . . . . . . . . . . . . . . 4 1.3.1 Low Power Wireless Standards . . . . . . . . . . . . . . . . . . . . 4 1.4 Low-Power Wireless Transceiver systems . . . . . . . . . . . . . . . . . . . 6 1.4.1 Survey of the previous work . . . . . . . . . . . . . . . . . . . . . . 7 1.4.2 The Designed Transmitter System . . . . . . . . . . . . . . . . . . 8 1.5 Ultra-Low Power Transmitters Performance Metrics . . . . . . . . . . . . 9 1.6 Thesis Contribution and Outline . . . . . . . . . . . . . . . . . . . . . . . 10 2 Circuit Design for The Transmitter 11 2.1 Technology Characterization and Modeling for Low-Power Designs . . . 11 2.1.1 Passive Components modeling . . . . . . . . . . . . . . . . . . . . 11 2.1.2 Active Components Modeling . . . . . . . . . . . . . . . . . . . . . 13 2.1.3 MOS Transistor Sub-threshold Modeling . . . . . . . . . . . . . . 13 2.1.4 MOS Transistor Simulation-Based Modeling . . . . . . . . . . . . . 14 2.2 Low-Voltage Low-Power Analog and RF Design Principles . . . . . . . . . 17 2.2.1 Separate Gate Biasing of The Inverter . . . . . . . . . . . . . . . . 17 2.2.2 Body Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3 Low-Voltage Analog Mixed Biasing Circuit Designs . . . . . . . . . . . . . 18 2.3.1 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.2 Operational Amplifier Design . . . . . . . . . . . . . . . . . . . . . 19 2.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4.1 The MEMS Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4.2 Crystal Oscillator Topologies . . . . . . . . . . . . . . . . . . . . . 23 2.4.3 Design of The CMOS Crystal Oscillator . . . . . . . . . . . . . . . 26 2.5 Pre-Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.6 OOK Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.7 BPSK Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.8 Digital Control of the Modulators . . . . . . . . . . . . . . . . . . . . . . . 35 2.9 Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.9.1 ULP PA Topologies Survey . . . . . . . . . . . . . . . . . . . . . . 38 2.9.2 The Push-Pull PA Design Methodology . . . . . . . . . . . . . . . 41 2.10 Transmit/Receive (T/R) Switch . . . . . . . . . . . . . . . . . . . . . . . 43 2.10.1 T/R Switch Topologies . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.10.2 Suggested Low-Area Low-Voltage RF Switch . . . . . . . . . . . . 46 3 Transmitter Integration and Final Results 48 3.1 Transmitter Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.2 Transmitter Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.3 Results Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.4 Results Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4 Conclusions 59 4.1 Thesis Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 A Bond Wire Parasitic Modeling 61 B Crystal Oscillator With Parasitic Effects 67 B.1 Simulation of FBAR with Parasitic Effects . . . . . . . . . . . . . . . . . 67 B.2 Root Locus Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Bibliography 7

Co-design of a Class-D Oscillator and Dedicated DC-DC Power Converter

openL'obiettivo di questa tesi è stato lo sviluppo di un oscillatore in Classe-D direttamente alimentato da un convertitore DC/DC. Inoltre, è stata esplorata la possibilità di utilizzare il segnale di uscita fornito dall'oscillatore per fornire il segnale di switching al convertitore. I vari componenti del circuito sono stati analizzati concentrandosi sulle sfide progettuali di ciascun componente, sulla loro interazione reciproca e cercando, se possibile, di ottenere un circuito completamente integrato. Alcune possibili soluzioni vengono poi fornite alla fine della tesi, compresi i risultati delle simulazioni per i circuiti presentati.This thesis analyses the design problems behind the realization of an integrated oscillator directly powered by a switching voltage regulator. Additionally, the possibility of using the oscillator itself to provide the switching frequency for the converter is explored. The building blocks constituting the circuit are analysed focusing on the different design challenges of each component, on how they interact with each other and if it is possible to obtain a fully integrated design. Some possible design solutions are then provided at the end of the thesis including simulation results for the presented circuits

Millimetre-wave optically injection-locked oscillators for radio-over-fibre systems

Theoretical analysis and experimental results for millimetre-wave optically injection-locked oscillators are presented in this thesis. Such oscillators can be employed to replace conventional photodiode plus amplifier receivers for local oscillator signal reception in millimetre-wave radio-over-fibre systems. The theories for electrical injection-locked oscillators are reviewed in detail. Three differences between Adler’s and Kurokawa’s equations for locking bandwidth are highlighted for the first time. These differences are the absence of l/cos# factor in Adler’s equation, larger bandwidth predicted by Kurokawa’s equation, and a difference in definition of Q factors. Locking bandwidth equations for optically injection-locked oscillators are developed based on the theories of electrical injection-locked oscillators and are then used to design optically injection-locked oscillators. A novel millimetre-wave indirect optically injection-locked oscillator is presented. An edge-coupled photodiode is used to detect the optical signal. Negative resistance and computer simulation techniques were used for predicting the free running oscillation frequency. The maximum output power of the oscillator is 5.3 dBm, and the maximum locking bandwidth is measured to be 2.6 MHz with an output power o f-12 dBm. Results from a comparison with conventional optical receivers show that the gain of the optically injection-locked oscillator is more than 10 dB higher than that of a photodiode plus amplifier receiver, that the oscillator output power remains constant with input signal power variations whereas the output power of the photodiode plus amplifier receiver changes (linearly) with the input signal power, and that, at high-offset frequencies, the phase noise of the optically injection-locked oscillator is much lower than that of the photodiode plus amplifier receiver. These advantages make the optically injection-locked oscillator an ideal replacement for the photodiode plus amplifier receiver in radio-over-fibre systems. An improved wide-band design for millimetre-wave optically injection-locked oscillators is presented for future work

Design and realization of fully integrated multiband and multistandard bi-cmos sigma delta frequency synthesizer

Wireless communication has grown, exponentially, with wide range of applications offered for the customers. Among these, WLAN (2.4-2.5GHz, 3.6-3.7GHzand 4.915- 5.825GHz GHz), Bluetooth (2.4 GHz), and WiMAX (2.500-2.696 GHz, 3.4-3.8 GHz and 5.725-5.850 GHz) communication standard/technologies have found largest use local area, indoor – outdoor communication and entertainment system applications. One of the recent trends in this area of technology is to utilize compatible standards on a single chip solutions, while meeting the requirements of each, to provide customers systems with smaller size, lower power consumption and cheaper in cost. In this thesis, RF – Analog, and – Digital Integrated Circuit design methodologies and techniques are applied to realize a multiband / standart (WLAN and WiMAX) operation capable Voltage- Controlled-Oscillator (VCO) and Frequency Synthesizer. Two of the major building blocks of wireless communication systems are designed using 0.35 μm, AMS-Bipolar (HBT)-CMOS process technology. A new inductor switching concept is implemented for providing the multiband operation capability. Performance parameters such as operating frequencies, phase noise, power consumption, and tuning range are modeled and simulated using analytical approaches, ADS® and Cadence® design and simulation environments. Measurement and/or Figure-of-Merit (FOM) values of our circuits have revealed results that are comparable with already published data, using the similar technology, in the literature, indicating the strength of the design methodologies implemented in this study