High Performance Tunable Active Inductors For Microwave Circuits

Tez (Doktora) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2016Thesis (PhD) -- İstanbul Technical University, Institute of Science and Technology, 2016RF uygulamalarında enduktif karakteristiğe önemli ölçüde ihtiyaç duyulmaktadır; bunlar, özellikle filtreler, düşük gürültülü yükselteçler (LNA, low noise amplifiers), gerilim kontrollü osilatörler (VCO, voltage controlled oscillators), pek çok farklı türde yükselteç için band genişliği iyileştirilmesi, faz kaydırıcılar, güç bölücüler ve eşleştirme (matching) devreleri vb. uygulamalardır. Pasif sarmal çip-içi CMOS endüktansların eksik yönleri ayrıntılı olarak literatürde tartışılmıştır. Bu tür endüktanslar düşük değer katsayısı (quality factor), düşük öz-rezonans frekansı (SRF, self-resonance frequency), sabit ve düşük değerli endüktans ve geniş bir silikon (silicon) alanı gerektirmeleri gibi istenmeyen özelliklere sahiptirler. Diğer yandan, MOS transistorlar kullanılarak sentezlenen CMOS aktif endüktansların, pasif sarmal eşdeğer yapıları ile karşılaştırıldığında pek çok çekici karakteristik özellik sunabildikleri gösterilmiştir. Bunlar; geniş bir bölgede ayarlanabilir öz-rezonans frekansı başarımı, geniş bir bölgede ayarlanabilir endüktans başarımı, geniş bir bölgede ayarlanabilir değer katsayısı başarımı, CMOS teknolojileri ile tümüyle gerçeklenebilme ve az alan kaplama gibi karakteristik özellikleri olarak ortaya konulmaktadır. Literatürde jiratör-C (GC) prensibi, topolojisi, karakterizasyonu ve uygulamaları ayrıntılı olarak ele alınmaktadır. İşlemsel geçiş-iletkenliği kuvvetlendiricisi (OTA, operational transconductance amplifier) ile gerçeklenen GC devreleri, RF uygulamaları için oldukça uygundur. Bu özellik, GC yapılarının söz konusu yapı kullanılarak en az sayıda aktif eleman ile gerçeklenebilmesinden kaynaklanmaktadır. Gerek topraklı (grounded) gerekse yüzen (floating) aktif endüktansların GC devreleri ile gerçeklenebildiği gösterilmiştir. Aktif endüktansların başarımlarının nicel olarak ölçülmesi amacıyla, çok sayıda ölçüt ortaya konulmuştur. Bu ölçütler frekans çalışma aralığı, endüktans ayarlanabilirliği, değer katsayısı, gürültü ve güç tüketimi gibi temel özellikleri içerirler. CMOS transistorların parazitik bileşenlerinden dolayı tasarlanan aktif endüktanslar belirli bir frekans bölgesinde endüktif davranış gösterirler. Alt frekans sınırı, GC devrelerinin sıfır frekansı ile belirlenirken; üst frekans sınırı ise öz-rezonans frekansı ile belirlenir. Aktif endüktansların pasif sarmal eşdeğer yapılarına göre en önemli üstünlüklerinden biri de; endüktanslarının geniş bir değer aralığıunda ayarlanabilir olmasıdır. GC aktif endüktansların endüktans değeri, transistorların geçiş-iletkenliklerinin ya da MOS varaktörlerle gerçeklenen yük kapasitanslarının değiştirilmesi ile ayarlanabilir. Literatürde, GC topolojisine dayalı pek çok CMOS AI (active inductor) devresi bildirilmiştir. Bunların tümü, farklı teknikler kullanılarak yüksek başarımlı AI yapıları oluşturmayı amaçlamışlardır. Bu tezde, bunlardan güncel olan bazı GAI (grounded AI) ve FAI (floating AI) yapıları gözden geçirilmiştir. Bunlardan bazıları, değer katsayısını (QF) iyileştirmek amacıyla, AI kaybını telafi etmek için negatif direnç kullanmışlardır. GC yapıları RF uygulamaları için tasarlandıklarında en az sayıda transistor kullanımı çok kritiktir. Çünkü bu durum AI öz-rezonans frekansının artmasına yardımcı olur. AI’ler, kazanç artırma amacıyla LNA’lerde geniş kullanım alanı bulabilmektedirler. Diğer taraftan, AI yapılarının en önemli dezvantajlarından biri gürültü başarımının pasif endüktanslara nispeten yüksek olmasıdır. Literatürde bu dezavantajı gidermek amacıyla teklif edilen yaklaşımlardan biri dejenerasyon direncinin bulunduğu bir geribesleme katı kullanılarak girişe gelen gürültü katkısını azaltmayı amaçlamıştır. Literatürde teklif edilen tekniklerin amacı, parazitik bileşenlerin etkisini azaltmak ya da tümüyle ortadan kaldırmaktır. Bu tezde, ileri devre teknikleri kullanılarak, yeni topraklı (grounded) ve yüzen (floting) AI yapıları tasarlanmıştır. AI giriş ve çıkış düğümlerine ait iletkenlikleri azaltmak için çoklu-düzenlenmiş kaskod (multi-regulated cascode, MRC) katları QF değerini iyileştirme amacıyla kullanılmaktadır. MRC katı PMOS transistorlarıyla oluşturulmuştur. PMOS transistor kullanımı, • ikinci kat kutuplamasını ayarlayabilmek amacıyla, giriş transistor boyutunun mümkün olduğunca azaltılmasını, • ana AC işaret yolundaki transistor sayısının azaltılmasını, sağlamaktadır. Tezde sunulan teorik analiz ve serim sonrası benzetim sonuçları, MRC katı kullanımının AI özelliklerine yaptığı etkiyi göstermektedir. Elde edilen sonuçlar bu katların AI tasarımında yüksek QF elde edilmesini imkan tanıdığını ortaya koynaktadır. Literatürde, iki ana AI başarım karakteristiği olan SRF ve QF başarımlarının iyileştirmesi için çok sayıda çalışma bulunmaktadır. Bu tezde, birbirlerini etkilemeksizin SRF ve QF başarımlarının ayarlanabilmesi özelliğine sahip bir AI’ın tasarımı ve benzetgimi yapılmıştır. Kaskod ve RC geribesleme yapıları yeni AI tasarımında kullanılmıştır. Daha önce de tartışıldığı üzere, AI karakterizasyonu açısından giriş transistoru çok önemlidir. Girişi transistorunun kaskodlanması, ilk jiratörün geçiş-iletkenliğinin ve giriş parazitik kapasitansının birbirinden bağımsız olarak ayarlanması gibi önemli ve kullanışlı bir özelliği beraberinde getirir. Bunun yanısıra, endüktansın değeri diğer transistorun iletkenliği ile ayarlanabilir. AI parazitik seri-rezistansını yok etmek amacıyla kullanılan RC geribeslemesi, QF iyileştirmesini sağlayabilmektedir. Kaskod transistorların kutuplama koşulu bir diyot-bağlı transistor ile sağlandığından; önerilen yapı proses, gerilim ve sıcaklık değişimleri açısından kararlı ve yüksek başarımlıdır. AI yapılarında karşılaşılan düşük gürültü başarımı, AI’ların LNA gibi RF uygulamalarda kullanımını sınırlamaktadır. Bir AI’ın ana gürültü kaynağı giriş transistorudur. Düşük gürültülü AI elde etmek için, giriş transistoru yeterince büyük boyutlu olarak tasarlanmalıdır. Ne var ki, büyük boyutlu böyle bir transistor, düşük bir SRF ve dolayısıyla sınırlı bir endüktif bandı beraberinde getirir. Bu tezde, düşük gürültülü ve az kayıplı uygun bir AI, düşük gürültü gerektiren RF uygulamaları için sunulmuştur. Teklif edilen AI devresindeki tüm transistorların ortak-kaynak (common-source, CS) yapısında kullanılması, düşük iletkenliğe sahip düğümlerin dolayısıyla yüksek QF değerine sahip bir AI’ın elde edilmesine olanak sağlamaktadır. AI gürültüsünü azaltmak için, sırasıyla P-tipi MOS transistorlar ve ileri-besleme yolu yapısı (feed-forward path, FFP) kullanılmaktadır. Bilindiği gibi, sensörler çok çeşitli fiziksel büyüklüklerin eletrik mühendisiliği alanına taşınmasını sağlamaktadır. Çok geniş kullanım alanı bulan sensör tiplerinden biri kapasitif mikro algılıyıcılardır. Kapasitif mikro algılayıcılar mekanik hareketleri küçük kapasitans değişimlerine çevirirler. Micro algılayıcıdaki kapasitans değişimi femto-Farad mertebesinde olup algılamayı zorlaştırmaktadır. Diğer yandan, küçük bir kapasitans değişimini yüksek bir empedans değişimine çevirebilmeleri dolayısıyla, GC topolojilerinin kapasitif algılayıcılarda kullanılabileceğini söylemek mümkündür. Bu tezde, bu düşünceden yola çıkılarak, kesit duyarlılığını yok etme yeteneğine sahip yeni bir 3-eksen ivme-ölçer tasarlanmıştır. Yapının, her eksendeki ivmeyi bağımsız olarak algılayabilmesi için, algılayıcı elektrodları uygun olarak yerleştirilmiştir. Daha sonra, bir kapasitif algılayıcıdaki çok küçük kapasitans değişimlerini algılayabilmek için yeni bir GC yapısı teklif edilmiştir. Önerilen yapıda, çalışma frekansı aralığı ve ölçekleme çarpanı, kutuplama akımlarının ayarlanması suretiyle birbirini etkilemeksizin ayarlanabilmektedir. Ayrıca, önerilen yapıda, parazitik bileşenlerin etkisini yok etmek için RC geribesleme ve kaskod yapılar kullanılmaktadır. Son olarak, bu tezde sunulan AI’ların çok amaçlı özellikte olduğunu göstermek amacıyla, 3 ve 6. dereceden geniş bantlı mikrodalga filtrelerde kullanılmaları ele alınmıştır. İlki 3. dereceden bir Chebyshev alçak geçiren filtredir. Basitleştirilmiş gerçel frekans tekniği (SRFT, simplified real frequency technique) ile tasarlanan ikincisi ise, 6. dereceden bir Chebyshev band geçiren filtredir. Filtrelerin benzetimle elde edilmiş frekans yanıtları, bu tezde sunulan AI’ların literatürdeki yapılara güçlü birer alternatif olduklarını ortaya koymaktadır.There is critical need for inductive characteristics in RF applications, especially in filters, LNA, VCO, bandwidth-enhancement in many kinds of amplifiers, phase shifters, power divider and matching networks. The drawbacks of using passive and spiral inductors in CMOS process are discussed in the literature. It is shown that these kind of inductors suffer from a low quality factor, a low self-resonant frequency, a low and fixed inductance value and the need for a large silicon area. Furthermore, it is shown in the literature that CMOS Active Inductors (AIs), which are synthesized using MOS transistors, offer a number of attractive characteristics as compared with their spiral counterparts. These characteristics include a low silicon consumption, a large and tunable self-resonant frequency, a large and tunable inductance, a large and tunable quality factor, and fully realizable in digital CMOS technologies. Then principles, topologies, characterizations and implementation of the Gyrator-C (GC) network is discussed in-depth. The GC networks, which are implemented by operational transconductance amplifier, are suitable for RF application. This property arises from their minimum usage of active elements. It is shown that both grounded and floating active inductors can be implemented by GC networks. To provide a quantitative measure of the performance of AIs, a number of figure-of-merits have been introduced in the thesis. These figure-of-merits include frequency range, inductance tunability, quality factor, noise and power consumption. Due to parasitic components of CMOS transistors, designed AIs have inductive behavior in a specified frequency range. The low frequency bound is set by the frequency of the zero of the gyrator-C networks while the upper frequency bound is set by Self-Resonance Frequency (SRF). One of the key advantages of active inductors over their spiral counterparts is the large tunability of their inductance. The inductance of GC AIs can be tuned by varying either the transconductances of the transconductors or the load capacitance, which is implemented by MOS varactor. Based on GC topology, there are many reported CMOS AI circuits in literature. All of them have tried to invent high performance AI by using different techniques. Some of recent proposed Grounded AI (GAI) and Floating AI (FAI) circuits are reviewed in the thesis. Some of them use negative resistor to compensate the loss of AI for QF enhancement. Some others try to use minimum number of transistors in order to increase the self-resonance frequency of AI for RF applications. In some applications, AIs are used in LNA circuits for gain boosting purpose. In that applications, designers have tried to cancel the noise of AI by using a feedback stage with a degeneration resistor to reduce the noise contribution to the input. The main aim of all the techniques is to cancel or reduce the effects of parasitic components. In the thesis, four new grounded and floating AIs are designed by using advanced circuit techniques. The first one, Multi Regulated Cascode (MRC) stages are employed for lowering conductance in input and output nodes of AI. Thus, Q performance is improved. Since these stages are used only for increasing impedance of input/output nodes, they are made up of PMOS transistors in order to: • minimize the input transistor as small as possible in order to adjust second stage biasing, • decrease the number of transistors in main path of AC signal Theoretical analysis and post-layout simulation results shows the effectiveness of using MRC stages usage in properties of AI. High Q symmetric floating version of low loss inductor is also designed by utilizing MRC stages. Designers do their best to improve SRF and QF, two main characteristics in term of AI performance. An AI with ability to adjust its SRF and QF without affecting each other is designed and simulated as a third. The cascoding and RC feedback structures are used in the new design of AI. As it discussed before, input transistor is very important regarding to AI characterizations. Cascoding input transistor gives the ability to adjust the first gyrator’s transconductance and input parasitic capacitance independently which it results in adjusting the self-resonance frequency and quality factor separately. Due to our best knowledge from literature reviewing, it is first time that the properties of an inductor can be adjusted independently. Furthermore, the inductance value can be adjusted by other transistor’s transconductances. Also, the RC feedback is utilized to cancel the parasitic series-resistance of AI which results in QF enhancement. Since, bias condition of cascoding transistors is provided by a diode-connected transistor, the proposed structure is robust in terms of performance over variation in process, voltage and temperature. The Noise of designed AIs has limited the use of them in RF applications such as LNAs. The main noise source of an AI is its input transistor. In order to have low noise AI, the input transistor should be designed large enough. But it leads to low SRF which limited the inductive frequency band. As a fourth active inductor design, a low-noise and low-loss AI is presented suitable for RF low noise applications. Utilizing all transistors in Common Sourse (CS) configuration on the AI circuit leads to low conductance nodes which causes the AI to have high Q. P-type MOS transistors and Feed-Forward Path (FFP) are employed to decrease noise of the AI, respectively. The GC topologies can convert a low capacitance variation to high impedance changing which makes it a good choice for capacitive sensors. The capacitive based micro sensors convert mechanical signals to small capacitance variation. The capacitance variation in micro sensor is in the range of femto-Farads which makes it difficult to sense. Thus, the GC topologies can be used in capacitive sensors in order to sense small capacitive variations. In the thesis, this technique is used in a new accelerometer sensor. It is first time that a gyrator-C network is employed as an interface circuit for capacitive change detection in micro sensors. The new accelerometer structure is designed by using with ability to cancel cross section sensitivity. The sensor’s electrodes are located in such a way that enables the structure to detect acceleration in 3-axis independently. Embedding all 3-axis detecting electrodes in a single proof mass and ability to detect acceleration orientation are salient features of the proposed sensor. Consequently, a new GC configuration for sensing very small capacitance changes in a capacitive sensor is presented in the thesis. In the proposed configuration, the operating frequency range and scaling factor can be adjusted without affecting each other by tuning the bias currents of utilized gyrators. In addition, the proposed configuration employs RC feedback together with the cascoding technique to cancel the effect of the parasitic components in order to get accurate scaling from gyrator-C network. Finally, in order to show versatility of designed AIs, they are used in designed third and sixth order broadband microwave filters. The first one is a third order Chebyshev low pass filter. The second one, which is designed by using simplified real frequency technique is a sixth order Chebyshev band pass filter. The simulated frequency response of filters prove the workability of the designed AIs.DoktoraPh

Design of Analog & Mixed Signal Circuits in Continuous-Time Sigma-Delta Modulators for System-on-Chip applications

Software-defined radio receivers (SDRs) have become popular to accommodate multi-standard wireless services using a single chip-set solution in mobile telecommunication systems. In SDRs, the signal is down-converted to an intermediate frequency and then digitalized. This approach relaxes the specifications for most of the analog front-end building blocks by performing most of the signal processing in the digital domain. However, since the analog-to-digital converter (ADC) is located as close as possible to the antenna in SDR architectures, the ADC specification requirements are very stringent because a large amount of interference signals are present at the ADC input due to the removal of filtering blocks, which particularly affects the dynamic range (DR) specification. Sigma-delta (ΣΔ) ADCs have several benefits such as low implementation cost, especially when the architecture contains mostly digital circuits. Furthermore, continuous-time (CT) ΣΔ ADCs allow elimination of the anti‐aliasing filter because input signals are sampled after the integrator. The bandwidth requirements for the amplifiers in CT ΣΔ ADCs can be relaxed due to the continuous operation without stringing settling time requirements. Therefore, they are suitable for high‐speed and low‐power applications. In addition, CT ΣΔ ADCs achieve high resolution due to the ΣΔ modulator’s noise shaping property. However, the in-band quantization noise is shaped by the analog loop filter and the distortions of the analog loop filter directly affect the system output. Hence, highly linear low-noise loop filters are required for high-performance ΣΔ modulators. The first task in this research focused on using CMOS 90 nm technology to design and fabricate a 5^(TH)–order active-RC loop filter with a cutoff frequency of 20 MHz for a low pass (LP) CT ΣΔ modulator. The active-RC topology was selected because of the high DR requirement in SDR applications. The amplifiers in the first stage of the loop filter were implemented with linearization techniques employing anti-parallel cancellation and source degeneration in the second stage of the amplifiers. These techniques improve the third-order intermodulation (IM3) by approximately 10 dB; while noise, area, and power consumption do not increase by more than 10%. Second, a current-mode adder-flash ADC was also fabricated as part of a LP CT ΣΔ modulator. The new current-mode operation developed through this research makes possible a 53% power reduction. The new technology also lessens existing problems associated with voltage-mode flash ADCs, which are mainly related to voltage headroom restrictions, speed of operation, offsets, and power efficiency of the latches. The core of the current-mode adder-flash ADC was fabricated in CMOS 90 nm technology with 1.2 V supply; it dissipates 3.34 mW while operating at 1.48 GHz and consumes a die area of 0.0276 mm^(2). System-on chip (SoC) solutions are becoming more popular in mobile telecommunication systems to improve the portability and competitiveness of products. Since the analog/RF and digital blocks often share the same external power supply in SoC solutions, the on-chip generation of clean power supplies is necessary to avoid system performance degradation due to supply noises. Finally, the critical design issues for external capacitor-less low drop-out (LDO) regulators for SoC applications are addressed in this dissertation, especially the challenges related to power supply rejection at high frequencies as well as loop stability and transient response. The paths of the power supply noise to the LDO output were analyzed, and a power supply noise cancellation circuit was developed. The power supply rejection (PSR) performance was improved by using a replica circuit that tracks the main supply noise under process-voltage-temperature variations and all operating conditions. Fabricated in a 0.18 μm CMOS technology with 1.8 V supply, the entire proposed LDO consumes 55 μA of quiescent current while in standby operation, and it has a drop-out voltage of 200 mV when providing 50 mA to the load. Its active core chip area is 0.14 mm2. Compared to a conventional uncompensated LDO, the proposed architecture presents a PSR improvement of 34 dB and 25 dB at 1 MHz and 4 MHz, respectively

Measurements, Models, Systems and Design

531 s.

Advanced Trends in Wireless Communications

Physical limitations on wireless communication channels impose huge challenges to reliable communication. Bandwidth limitations, propagation loss, noise and interference make the wireless channel a narrow pipe that does not readily accommodate rapid flow of data. Thus, researches aim to design systems that are suitable to operate in such channels, in order to have high performance quality of service. Also, the mobility of the communication systems requires further investigations to reduce the complexity and the power consumption of the receiver. This book aims to provide highlights of the current research in the field of wireless communications. The subjects discussed are very valuable to communication researchers rather than researchers in the wireless related areas. The book chapters cover a wide range of wireless communication topics

Biomimetic cochlea filters : from modelling, design to analogue VLSI implementation

This thesis presents a novel biomimetic cochlea filter which closely resembles the biological cochlea behaviour. The filter is highly feasible for analogue very-large-scale integration (VLSI) circuits, which leads to a micro-watt-power and millimetre-sized hardware implementation. By virtue of such features, the presented filter contributes to a solid foundation for future biologically-inspired audio signal processors. Unlike existing works, the presented filter is developed by taking direct inspirations from the physiologically measured results of the biological cochlea. Since the biological cochlea has prominently different characteristics of frequency response from low to high frequencies, the biomimetic cochlea filter is built by cascading three sub-filters accordingly: a 2nd-order bandpass filter for the constant gentle low-frequency response, a 2nd-order tunable low-pass filter for the variable and selective centre frequency response and a 5th-order elliptic filter for the ultra-steep roll-off at stop-band. As a proof of concept, a biomimetic cochlea filter bank is built to process audio signals, which demonstrates the highly discriminative spectral decomposition and high-resolution time-frequency analysis capabilities similar to the biological cochlea. The filter has simple representation in the Laplace domain which leads to a convenient analogue circuit realisation. A floating-active-inductor circuit cell is developed to build the corresponding RLC ladder for each of the three sub-filters. The circuits are designed based on complementary metal-oxide-semiconductor (CMOS) transistors for VLSI implementation. Non-ideal factors of CMOS transistors including parasitics, noise and mismatches are extensively analysed and consciously considered in the circuit design. An analogue VLSI chip is successfully fabricated using 0.35μ m CMOS process. The chip measurements demonstrate that the centre frequency response of the filter has about 20 dB wide gain tuning range and a high quality factor reaching maximally over 19. The filter has a 20 dB/decade constant gentle low-frequency tail and an over 300 dB/decade sharp stop-band roll-off slope. The measured results agree with the filter model expectations and are comparable with the biological cochlea characteristics. Each filter channel consumes as low as 59.5 ~90μ Wpower and occupies only 0.9 mm2 area. Besides, the biomimetic cochlea filter chip is characterised from a wide range of angles and the experimental results cover not only the auditory filter specifications but also the integrated circuit design considerations. Furthermore, following the progressive development of the acoustic resonator based on microelectro- mechanical systems (MEMS) technology, a MEMS-CMOS implementation of the proposed filter becomes possible in the future. A key challenge for such implementation is the low sensing capacitance of the MEMS resonator which suffers significantly from sensitivity degradation due to the parasitic capacitance. A novel MEMS capacitive interface circuit chip is additionally developed to solve this issue. As shown in the chip results, the interface circuit is able to cancel the parasitic capacitance and increase the sensitivity of capacitive sensors by 35 dB without consuming any extra power. Besides, the chopper-stabilisation technique is employed which effectively reduces the circuit flicker noise and offsets. Due to these features, the interface circuit chip is capable of converting a 7.5 fF capacitance change of a 1-Volt-biased 0.5 pF capacitive sensor pair into a 0.745 V signal-conditioned output while consuming only 165.2μ W power

The 1991 3rd NASA Symposium on VLSI Design

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2

Circuit-aware system design techniques for wireless communication

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (p. 211-218).When designing wireless communication systems, many hardware details are hidden from the algorithm designer, especially with analog hardware. While it is difficult for a designer to understand all aspects of a complex system, some knowledge of circuit constraints can improve system performance by relaxing design constraints. The specifications of a circuit design are generally not equally difficult to meet, allowing excess margin in one area to be used to relax more difficult design constraints. We first propose an uplink/downlink architecture for a network with a multiple antenna central server. This design takes advantage of the central server to allow the nodes to achieve multiplexing gain by forming virtual arrays without coordination, or diversity gain to decrease SNR requirements. Computation and memory are offloaded from the nodes to the server, allowing less complex, inexpensive nodes to be used. We can further use this SNR margin to reduce circuit area and power consumption, sacrificing system capacity for circuit optimization. Besides the more common transmit power reduction, large passive analog components can be removed to reduce chip area, and bias currents lowered to save power at the expense of noise figure. Given the inevitable crosstalk coupling of circuits, we determine the minimum required crosstalk isolation in terms of circuit gain and signal range.(cont.) Viewing the crosstalk as a static fading channel, we derive a formula for the asymptotic SNR loss, and propose phase randomization to reduce the strong phase dependence of the crosstalk SNR loss. Because the high peak to average power (PAPR) that results from multicarrier systems is difficult for analog circuits to handle, the result is low power efficiencies. We propose two algorithms, both of which can decrease the PAPR by 4 dB or more, resulting in an overall power reduction by over a factor of three in the high and low SNR regimes, when combined with an outphasing linear amplifier.by Everest Wang Huang.Ph.D

Circuit-Aware System Design Techniques for Wireless Communication

Thesis Supervisor: Gregory W. Wornell Title: ProfessorWhen designing wireless communication systems, many hardware details are hidden from the algorithm designer, especially with analog hardware. While it is difficult for a designer to understand all aspects of a complex system, some knowledge of circuit constraints can improve system performance by relaxing design constraints. The specifications of a circuit design are generally not equally difficult to meet, allowing excess margin in one area to be used to relax more difficult design constraints. We first propose an uplink/downlink architecture for a network with a multiple antenna central server. This design takes advantage of the central server to allow the nodes to achieve multiplexing gain by forming virtual arrays without coordination, or diversity gain to decrease SNR requirements. Computation and memory are offloaded from the nodes to the server, allowing less complex, inexpensive nodes to be used. We can further use this SNR margin to reduce circuit area and power consumption, sacrificing system capacity for circuit optimization. Besides the more common trans- mit power reduction, large passive analog components can be removed to reduce chip area, and bias currents lowered to save power at the expense of noise figure. Given the inevitable crosstalk coupling of circuits, we determine the minimum required crosstalk isolation in terms of circuit gain and signal range. Viewing the crosstalk as a static fading channel, we derive a formula for the asymptotic SNR loss, and propose phase randomization to reduce the strong phase dependence of the crosstalk SNR loss. Because the high peak to average power (PAPR) that results from multicarrier systems is difficult for analog circuits to handle, the result is low power efficiencies. We propose two algorithms, both of which can decrease the PAPR by 4 dB or more, resulting in an overall power reduction by over a factor of three in the high and low SNR regimes, when combined with an outphasing linear amplifier.MIT, the Semiconductor Research Corpo- ration and MARCO C2S2, and Lincoln Laboratory