Insulators for 2D nanoelectronics: the gap to bridge

Nanoelectronic devices based on 2D materials are far from delivering their full theoretical performance potential due to the lack of scalable insulators. Amorphous oxides that work well in silicon technology have ill-defined interfaces with 2D materials and numerous defects, while 2D hexagonal boron nitride does not meet required dielectric specifications. The list of suitable alternative insulators is currently very limited. Thus, a radically different mindset with respect to suitable insulators for 2D technologies may be required. We review possible solution scenarios like the creation of clean interfaces, production of native oxides from 2D semiconductors and more intensive studies on crystalline insulators

Scaling and variability in ultra thin body silicon on insulator (UTB SOI) MOSFETs

The main objective of this thesis is to perform a comprehensive simulation study of the statistical variability in well scaled fully depleted ultra thin body silicon on insulator (FD-UTB SOI) at nanometer regime. It describes the design procedure for template FDUTB SOI transistor scaling and the impacts of statistical variability and reliability the scaled template transistor. The starting point of this study is a systematic simulation analysis based on a welldesigned 32nm thin body SOI template transistor provided by the FP7 project PULLNANO. The 32nm template transistor is consistent with the International Technology Roadmap for Semiconductor (ITRS) 2009 specifications. The wellestablished 3D ‘atomistic’ simulator GARAND has been employed in the designing of the scaled transistors and to carry out the statistical variability simulations. Following the foundation work in characterizing and optimizing the template 32 nm gate length transistor, the scaling proceeds down to 22 nm, 16 nm and 11 nm gate lengths using typically 0.7 scaling factor in respect of the horizontal and vertical transistor dimensions. The device design process is targeted for low power applications with a careful consideration of the impacts of the design parameters choice including buried oxide thickness (TBOX), source/drain doping abruptness (σ) and spacer length (Lspa). In order to determine the values of TBOX, σ, and Lspa, it is important to analyze simulation results, carefully assessing the impact on manufacturability and to consider the corresponding trade-off between short channel effects and on-current performance. Considering the above factors, TBOX = 10nm, σ = 2nm/dec and Lspa = 7nm have been adopted as optimum values respectively. iv The statistical variability of the transistor characteristics due to intrinsic parameter fluctuation (IPF) in well-scaled FD-UTB SOI devices is systematically studied for the first time. The impact of random dopant fluctuation (RDF), line edge roughness (LER) and metal gate granularity (MGG) on threshold voltage (Vth), on-current (Ion) and drain induced barrier lowering (DIBL) are analysed. Each principal sources of variability is treated individually and in combination with other variability sources in the simulation of large ensembles of microscopically different devices. The introduction of highk/ metal gate stack has improved the electrostatic integrity and enhanced the overall device performance. However, in the case of fully depleted channel transistors, MGG has become a dominant variability factor for all critical electrical parameters at gate first technology. For instance, σVth due to MGG increased to 41.9 mV at 11nm gate length compared to 26.0 mV at 22nm gate length. Similar trend has also been observed in σIon, increasing from 0.065 up to 0.174 mA/μm when the gate length is reduced from 22 nm down to 11 nm. Both RDF and LER have significant role in the intrinsic parameter fluctuations and therefore, none of these sources should be overlooked in the simulations. Finally, the impact of different variability sources in combination with positive bias temperature instability (PBTI) degradation on Vth, Ion and DIBL of the scaled nMOSFETs is investigated. Our study indicates that BTI induced charge trapping is a crucial reliability problem for the FD-UTB SOI transistors operation. Its impact not only introduces a significant degradation of transistor performance, but also accelerates the statistical variability. For example, the effect of a late degradation stage (at trap density of 1e12/cm2) in the presence of RDF, LER and MGG results in σVth increase to 36.9 mV, 45.0 mV and 58.3 mV for 22 nm, 16 nm and 11 nm respectively from the original 29.0 mV, 37.9 mV and 50.4 mV values in the fresh transistors

Insulators for 2D nanoelectronics: the gap to bridge

Nanoelectronic devices based on 2D materials are far from delivering their full theoretical performance potential due to the lack of scalable insulators. Amorphous oxides that work well in silicon technology have ill-defined interfaces with 2D materials and numerous defects, while 2D hexagonal boron nitride does not meet required dielectric specifications. The list of suitable alternative insulators is currently very limited. Thus, a radically different mindset with respect to suitable insulators for 2D technologies may be required. We review possible solution scenarios like the creation of clean interfaces, production of native oxides from 2D semiconductors and more intensive studies on crystalline insulators

Strain-Engineered MOSFETs

This book brings together new developments in the area of strain-engineered MOSFETs using high-mibility substrates such as SIGe, strained-Si, germanium-on-insulator and III-V semiconductors into a single text which will cover the materials aspects, principles, and design of advanced devices, their fabrication and applications. The book presents a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization

Journal of Telecommunications and Information Technology, 2007, nr 2

kwartalni

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

Reliability-aware memory design using advanced reconfiguration mechanisms

Fast and Complex Data Memory systems has become a necessity in modern computational units in today's integrated circuits. These memory systems are integrated in form of large embedded memory for data manipulation and storage. This goal has been achieved by the aggressive scaling of transistor dimensions to few nanometer (nm) sizes, though; such a progress comes with a drawback, making it critical to obtain high yields of the chips. Process variability, due to manufacturing imperfections, along with temporal aging, mainly induced by higher electric fields and temperature, are two of the more significant threats that can no longer be ignored in nano-scale embedded memory circuits, and can have high impact on their robustness. Static Random Access Memory (SRAM) is one of the most used embedded memories; generally implemented with the smallest device dimensions and therefore its robustness can be highly important in nanometer domain design paradigm. Their reliable operation needs to be considered and achieved both in cell and also in architectural SRAM array design. Recently, and with the approach to near/below 10nm design generations, novel non-FET devices such as Memristors are attracting high attention as a possible candidate to replace the conventional memory technologies. In spite of their favorable characteristics such as being low power and highly scalable, they also suffer with reliability challenges, such as process variability and endurance degradation, which needs to be mitigated at device and architectural level. This thesis work tackles such problem of reliability concerns in memories by utilizing advanced reconfiguration techniques. In both SRAM arrays and Memristive crossbar memories novel reconfiguration strategies are considered and analyzed, which can extend the memory lifetime. These techniques include monitoring circuits to check the reliability status of the memory units, and architectural implementations in order to reconfigure the memory system to a more reliable configuration before a fail happens.Actualmente, el diseño de sistemas de memoria en circuitos integrados busca continuamente que sean más rápidos y complejos, lo cual se ha vuelto de gran necesidad para las unidades de computación modernas. Estos sistemas de memoria están integrados en forma de memoria embebida para una mejor manipulación de los datos y de su almacenamiento. Dicho objetivo ha sido conseguido gracias al agresivo escalado de las dimensiones del transistor, el cual está llegando a las dimensiones nanométricas. Ahora bien, tal progreso ha conllevado el inconveniente de una menor fiabilidad, dado que ha sido altamente difícil obtener elevados rendimientos de los chips. La variabilidad de proceso - debido a las imperfecciones de fabricación - junto con la degradación de los dispositivos - principalmente inducido por el elevado campo eléctrico y altas temperaturas - son dos de las más relevantes amenazas que no pueden ni deben ser ignoradas por más tiempo en los circuitos embebidos de memoria, echo que puede tener un elevado impacto en su robusteza final. Static Random Access Memory (SRAM) es una de las celdas de memoria más utilizadas en la actualidad. Generalmente, estas celdas son implementadas con las menores dimensiones de dispositivos, lo que conlleva que el estudio de su robusteza es de gran relevancia en el actual paradigma de diseño en el rango nanométrico. La fiabilidad de sus operaciones necesita ser considerada y conseguida tanto a nivel de celda de memoria como en el diseño de arquitecturas complejas basadas en celdas de memoria SRAM. Actualmente, con el diseño de sistemas basados en dispositivos de 10nm, dispositivos nuevos no-FET tales como los memristores están atrayendo una elevada atención como posibles candidatos para reemplazar las actuales tecnologías de memorias convencionales. A pesar de sus características favorables, tales como el bajo consumo como la alta escabilidad, ellos también padecen de relevantes retos de fiabilidad, como son la variabilidad de proceso y la degradación de la resistencia, la cual necesita ser mitigada tanto a nivel de dispositivo como a nivel arquitectural. Con todo esto, esta tesis doctoral afronta tales problemas de fiabilidad en memorias mediante la utilización de técnicas de reconfiguración avanzada. La consideración de nuevas estrategias de reconfiguración han resultado ser validas tanto para las memorias basadas en celdas SRAM como en `memristive crossbar¿, donde se ha observado una mejora significativa del tiempo de vida en ambos casos. Estas técnicas incluyen circuitos de monitorización para comprobar la fiabilidad de las unidades de memoria, y la implementación arquitectural con el objetivo de reconfigurar los sistemas de memoria hacia una configuración mucho más fiables antes de que el fallo suced

Advanced Silicon and Germanium Transistors for Future P-channel MOSFET Applications

Ph.DDOCTOR OF PHILOSOPH