Serial-parallel multiplication in Galois fields

A method for multiplying two elements from the Galois field GF(2 sup ms) is presented. This method provides a tradeoff between speed and complexity

Parallel multiplication and powering of polynomials

AbstractThis paper examines the most efficient known serial and parallel algorithms for multiplying and powering polynomials. For sparse polynomials the Simp algorithm multiplies using a simple divide and conquer approach, and the NOMC algorithm computes powers using a multinomial expansion. For dense polynomials the FFT multiplies and powers by evaluating polynomials at a set of points, performing pointwise multiplication or powering, and interpolating a polynomial through the results. Practical issues of applying these algorithms in algebraic manipulation systems are discussed

Efficient Bit-parallel Multiplication with Subquadratic Space Complexity in Binary Extension Field

Bit-parallel multiplication in GF(2^n) with subquadratic space complexity has been explored in recent years due to its lower area cost compared with traditional parallel multiplications. Based on \u27divide and conquer\u27 technique, several algorithms have been proposed to build subquadratic space complexity multipliers. Among them, Karatsuba algorithm and its generalizations are most often used to construct multiplication architectures with significantly improved efficiency. However, recursively using one type of Karatsuba formula may not result in an optimal structure for many finite fields. It has been shown that improvements on multiplier complexity can be achieved by using a combination of several methods. After completion of a detailed study of existing subquadratic multipliers, this thesis has proposed a new algorithm to find the best combination of selected methods through comprehensive search for constructing polynomial multiplication over GF(2^n). Using this algorithm, ameliorated architectures with shortened critical path or reduced gates cost will be obtained for the given value of n, where n is in the range of [126, 600] reflecting the key size for current cryptographic applications. With different input constraints the proposed algorithm can also yield subquadratic space multiplier architectures optimized for trade-offs between space and time. Optimized multiplication architectures over NIST recommended fields generated from the proposed algorithm are presented and analyzed in detail. Compared with existing works with subquadratic space complexity, the proposed architectures are highly modular and have improved efficiency on space or time complexity. Finally generalization of the proposed algorithm to be suitable for much larger size of fields discussed

Design and Characterization of Null Convention Self-Timed Multipliers

Self-timed multipliers, designed using the delay-insensitive null convention logic (NCL) paradigm, were analyzed. NCL require less power, generate less noise, produce less electromagnetic interference, and allow easier reuse of components. Simulation results show a large variance in circuit performance in terms of power, area, and speed. NCL paradigm also represent bit-serial, iterative, and fully parallel multiplication architectures. They reduce the effort required to ensure correct operation under all timing scenarios, compared to equivalent synchronous designs

Algorithms for Iterative Array Multiplication

Algorithms for the parallel multiplication of two n bit binary numbers by an iterative array of logic cells are discussed. The regular interconnection structures of the multiplier array cell elements, which are ideal for VLSI implementation, are described. The speed and hardware complexity of two new iterative array algorithms, both of which require n cell delays for one n by n bit multiplication, are compared with a straight-forward iterative array algorithm having a 2n cell delay and its higher radix version having an n cell delay

The scheduling of sparse matrix-vector multiplication on a massively parallel dap computer

An efficient data structure is presented which supports general unstructured sparse matrix-vector multiplications on a Distributed Array of Processors (DAP). This approach seeks to reduce the inter-processor data movements and organises the operations in batches of massively parallel steps by a heuristic scheduling procedure performed on the host computer. The resulting data structure is of particular relevance to iterative schemes for solving linear systems. Performance results for matrices taken from well known Linear Programming (LP) test problems are presented and analysed

IP-CORE OF HARDWARE MULTIPLIER OF INTEGER FOR VLSI FUNCTION-ORIENTED PROCESSOR

The article discusses using the algorithm for parallel multiplication of integers in two's complement code for increasing the speed of the multiplication in function-oriented processors. The results of prototyping a multiplier circuit using FPGA technology are presented