FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA Kernels

Using FPGAs as hardware accelerators that communicate with a central CPU is becoming a common practice in the embedded design world but there is no standard methodology and toolset to facilitate this path yet. On the other hand, languages such as CUDA and OpenCL provide standard development environments for Graphical Processing Unit (GPU) programming. FASTCUDA is a platform that provides the necessary software toolset, hardware architecture, and design methodology to efficiently adapt the CUDA approach into a new FPGA design flow. With FASTCUDA, the CUDA kernels of a CUDA-based application are partitioned into two groups with minimal user intervention: those that are compiled and executed in parallel software, and those that are synthesized and implemented in hardware. A modern low power FPGA can provide the processing power (via numerous embedded micro-CPUs) and the logic capacity for both the software and hardware implementations of the CUDA kernels. This paper describes the system requirements and the architectural decisions behind the FASTCUDA approach

SystemC Through the Looking Glass : Non-Intrusive Analysis of Electronic System Level Designs in SystemC

Due to the ever increasing complexity of hardware and hardware/software co-designs, developers strive for higher levels of abstractions in the early stages of the design flow. To address these demands, design at the Electronic System Level (ESL) has been introduced. SystemC currently is the de-facto standard for ESL design. The extraction of data from system designs written in SystemC is thereby crucial e.g. for the proper understanding of a given system. However, no satisfactory support of reflection/introspection of SystemC has been provided yet. Previously proposed methods for this purpose %introduced to achieve the goal nonetheless either focus on static aspects only, restrict the language means of SystemC, or rely on modifications of the compiler and/or parser. In this thesis, approaches that overcome these limitations are introduced, allowing the extraction of information from a given SystemC design without changing the SystemC library or the compiler. The proposed approaches retrieve both, static and dynamic (i.e. run-time) information

systemc based electronic system level design space exploration environment for dedicated heterogeneous multi processor systems

Abstract This work faces the problem of the Electronic System-Level (ESL) HW/SW co-design of dedicated electronic digital systems based on heterogeneous multi-processor architectures. In particular, the work presents a prototype SystemC-based environment that exploits a Design Space Exploration (DSE) approach able to suggest an HW/SW partitioning of the system specification and a mapping onto an automatically defined architecture. The descriptions of the reference HW/SW co-design methodology and the main design issues related to the developed DSE SW tools, supported by two reference use cases that allows to understand the role of the DSE step in the whole design flow, represent the core of the paper

The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration

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SystemC Model of Power Side-Channel Attacks Against AI Accelerators: Superstition or not?

As training artificial intelligence (AI) models is a lengthy and hence costly process, leakage of such a model's internal parameters is highly undesirable. In the case of AI accelerators, side-channel information leakage opens up the threat scenario of extracting the internal secrets of pre-trained models. Therefore, sufficiently elaborate methods for design verification as well as fault and security evaluation at the electronic system level are in demand. In this paper, we propose estimating information leakage from the early design steps of AI accelerators to aid in a more robust architectural design. We first introduce the threat scenario before diving into SystemC as a standard method for early design evaluation and how this can be applied to threat modeling. We present two successful side-channel attack methods executed via SystemC-based power modeling: correlation power analysis and template attack, both leading to total information leakage. The presented models are verified against an industry-standard netlist-level power estimation to prove general feasibility and determine accuracy. Consequently, we explore the impact of additive noise in our simulation to establish indicators for early threat evaluation. The presented approach is again validated via a model-vs-netlist comparison, showing high accuracy of the achieved results. This work hence is a solid step towards fast attack deployment and, subsequently, the design of attack-resilient AI accelerators

Rapid high-level behavioral modeling of soc communication interfaces

Abstract. The increasing complexity of hardware and software systems increases the amount of labour and resources required to model them. Especially in system-on-chips (SoC), the complexity of modeling is evident. Electronic system-level (ESL) modeling using the benefits of transaction level modeling (TLM) reduces the required resources and speeds up the modeling time. This thesis examines approximately timed modeling in the context of behavioral modeling with abstract processing elements and abstract arbitration procedures. This thesis describes the basic principles of SoC:s and TLM, and then a problem of modeling a SoC communication interface for a company is investigated, and a TLM solution to the modeling problem is explored.Järjestelmäpiirien tiedonsiirtoyhteyksien nopea korkean tason käytösmallinnus. Tiivistelmä. Laitteistojen ja systeemien kasvava kompleksisuus lisää niiden mallinnukseen vaadittua työmäärää ja resursseja. Erityisesti järjestelmäpiireissä (SoC) mallinnuksen monimutkaistuminen näkyy. Elektronisen järjestelmätason (ESL) mallinnus käyttämällä tapahtumatason mallinnuksen (TLM) hyötyjä vähentää vaadittuja resursseja ja nopeuttaa mallinnukseen kuluvaa aikaa. Tässä opinnäytetyössä tarkastellaan likimääräisesti ajastettua mallinnusta käytösmallinnuksen kontekstissa abstrakteilla prosessointi elementeillä ja abstrakteilla sovittelu proseduureilla. Tässä työssä kuvataan myös järjestelmäpiirin ja TLM:n perusperiaatteet, jonka jälkeen tutkitaan erään yrityksen SoC:in tiedonsiirtoväylän mallinnuksen ongelmaa, ja tutkitaan TLM ratkaisua mallinnusongelmalle