FVF-Based Low-Dropout Voltage Regulator with Fast Charging/Discharging Paths for Fast Line and Load Regulation

A new internally compensated low drop-out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65-nm CMOS technology. Measurements show load and line regulations of 433.80 μV/mA and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of 1 μs. The total current consumption is 17.88 μA (for a 0.9 V supply voltage).Ministerio de Economía y Competitividad TEC2015-71072-C3-3-RConsejería de Economía, Innovación y Ciencia. Junta de Andalucía P12-TIC-186

Ultra-low Quiescent Current NMOS Low Dropout Regulator With Fast Transient response for Always-On Internet-of-Things Applications

abstract: The increased adoption of Internet-of-Things (IoT) for various applications like smart home, industrial automation, connected vehicles, medical instrumentation, etc. has resulted in a large scale distributed network of sensors, accompanied by their power supply regulator modules, control and data transfer circuitry. Depending on the application, the sensor location can be virtually anywhere and therefore they are typically powered by a localized battery. To ensure long battery-life without replacement, the power consumption of the sensor nodes, the supply regulator and, control and data transmission unit, needs to be very low. Reduction in power consumption in the sensor, control and data transmission is typically done by duty-cycled operation such that they are on periodically only for short bursts of time or turn on only based on a trigger event and are otherwise powered down. These approaches reduce their power consumption significantly and therefore the overall system power is dominated by the consumption in the always-on supply regulator. Besides having low power consumption, supply regulators for such IoT systems also need to have fast transient response to load current changes during a duty-cycled operation. Supply regulation using low quiescent current low dropout (LDO) regulators helps in extending the battery life of such power aware always-on applications with very long standby time. To serve as a supply regulator for such applications, a 1.24 µA quiescent current NMOS low dropout (LDO) is presented in this dissertation. This LDO uses a hybrid bias current generator (HBCG) to boost its bias current and improve the transient response. A scalable bias-current error amplifier with an on-demand buffer drives the NMOS pass device. The error amplifier is powered with an integrated dynamic frequency charge pump to ensure low dropout voltage. A low-power relaxation oscillator (LPRO) generates the charge pump clocks. Switched-capacitor pole tracking (SCPT) compensation scheme is proposed to ensure stability up to maximum load current of 150 mA for a low-ESR output capacitor range of 1 - 47µF. Designed in a 0.25 µm CMOS process, the LDO has an output voltage range of 1V – 3V, a dropout voltage of 240 mV, and a core area of 0.11 mm2.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Regulador de rápido transitorio de bajo diferencial de tensión en tecnología de 90 nm

En este trabajo se presenta el diseño de un regulador lineal de bajo diferencial de tensión para aplicaciones portátiles. El circuito propuesto consiste de un esquema simple de amplificación con una etapa de ganancia más el transistor de potencia. Además, utiliza un espejo de corriente para sumar parte de la transconductancia de entrada a la salida y aumentar la ganancia sin carga de corriente. Las simulaciones realizadas en SYNOPSYS para una tecnología de 90 nm para el circuito diseñado muestran un desempeño robusto a variaciones de proceso, tensión y temperatura con un tiempo de establecimiento menor a 1μs. Además, la respuesta en frecuencia evidencia que se tiene una ganancia mínima de 43 dB y un rechazo a las variaciones de la fuente de entrada de -25 dB a 100 KHz. El consumo de potencia sin carga fue de 14 μA y puede entregar una corriente máxima de 25 mA.This paper presents the design of a low dropout linear regulator for portable applications. The proposed circuit consists of a simple amplification scheme with a single gain stage plus the power transistor.  Moreover, the circuit uses a current mirror to add part of input transconductance to the output, increasing the gain without load current. The simulations performed for the designed circuit in SYNOPSYS for a 90 nm technology show a robust performance to process, voltage and temperature variations with a settling time of 1μs. Also, the frequency response shows the minimum gain of 43 dB and a power supply rejection of -25 dB at 100 KHz. The power consumption without load current was 14 μA and it can deliver a maximum load current of 25 mA

Diseño de circuitos electrónicos de ultra-bajo consumo en tecnologías nanométricas

El escalado de los procesos de fabricación de semiconductores, predicho por el Dr. Moore en los años sesenta, ha tenido un gran impacto en el desarrollo de la electrónica integrada actual. Por una parte, la reducción del tamaño de los transistores ha permitido incrementar la densidad de integración, dando la posibilidad a los diseñadores de introducir un mayor número de funcionalidades dentro de una misma área. Por otro lado, este fenómeno ha llevado consigo una reducción de los costes asociados a la fabricación, logrando abaratar el producto final. Esta continua evolución e incremento de la funcionalidad dentro de un mismo circuito integrado, implica, a su vez, un aumento de la complejidad a la hora de planificar la generación y distribución de las distintas tensiones de alimentación, necesarias para cada uno de los bloques incluidos en el chip. Esto provoca que las especificaciones de ruido, regulación y/o estabilidad asociadas a cada dominio de alimentación varíen según la naturaleza del sistema al que se pretende alimentar. Por esta razón, los circuitos destinados a la gestión de la potencia han tomado una mayor relevancia en los últimos años, puesto que las restricciones impuestas por los sistemas integrados son cada vez mayores. Dentro de los circuitos destinados a la gestión de potencia, los reguladores lineales y, en concreto, los de bajo dropout se corresponden con un bloque básico, ya que permiten la generación de tensiones de alimentación muy estables, precisas y de bajo ruido. Estas características los convierten en el circuito ideal para alimentar a sistemas analógicos o de radio-frecuencia, muy sensibles a variaciones de la alimentación. Otra característica de estos bloques, que ha provocado el creciente interés de la comunidad científica en ellos, es la posibilidad de poder integrarlos sin necesidad de incluir ningún dispositivo externo, con el consecuente ahorro económico y de área en la tarjeta impresa. Sin embargo, dentro de los inconvenientes cabe destacar dos. Por una parte, la eficiencia máxima teórica que pueden lograr es baja frente a soluciones basadas en capacidades conmutadas o inductores. Por otro lado, al buscarse un esquema de compensación interna, el polo dominante del sistema viene fijado por un nodo interno del circuito, provocando que el polo no-dominante esté dominado por la carga. Esto se traduce en un gran problema de estabilidad, debido a que las variaciones que sufre la carga se traducen en un desplazamiento en frecuencia del polo no dominante, degradando el margen de fase de todo el sistema. Según lo descrito anteriormente, esta investigación se ha centrado en el estudio de reguladores lineales de tipo Low-DropOut o LDO compensados internamente y sus propiedades, dada la problemática de este tipo de celdas cuando se busca minimizar su consumo quiescente. Para ello, uno de los objetivos marcados versa sobre la búsqueda de topologías alternativas que permitan el diseño de LDOs de altas prestaciones, sin suponer un incremento del consumo quiescente y que sean válidos para entornos de baja tensión de alimentación. En este sentido, se ha apostado por el uso de la celda Flipped Voltage Follower como regulador debido a su baja impendancia de salida, gran estabilidad y sencillez. Una segunda línea, se ha centrado en la búsqueda de esquemas de compensación simples que permitan extender la estabilidad de este tipo de regulador en todo el rango de funcionamiento. Para ello, se ha explorado un esquema basado en la compensación clásica de Miller donde se ha utilizado un esquema de replica para ajustar de forma dinámica el valor de la resistencia según la carga del sistema. Por último, con el objetivo de minimizar lo máximo posible el consumo quiescente de los reguladores LDOs sin degradar las prestaciones de la respuesta transitoria, se ha explorado el uso de buffers clase AB para gestionar la puerta del transistor de paso. Esta técnica permite mejorar la respuesta transitoria, al ser capaz de crear corrientes elevadas durante las transiciones sin necesidad de penalizar la eficiencia del regulador.The continuous downscaling of semiconductor fabrication processes, which was predicted by PhD. Moore in 1965, have had a great impact in the development of nowadays integrated electronics. The reduction of transistor size has allowed, on one hand, the integration of more devices in the same área, increasing the integration density, while, on the other hand, has led to the reduction of fabrication costs, making the final product cheaper and accessible. However, this increase in the functionality of a single integrated circuit entails greater complexity in the generation and distribution of the different biasing voltages needed throughout one chip. Thus, as more different systems are integrated in the same chip, more different biasing domains coexists in it, leading several different requirements of noise, regulation and/or stability that need to be satisfied simultaneously. Therefore, power management circuits have been acquiring greater significance as technology downscales, reaching its maximum nowadays, when the nanoscale had taken those issues to its culmen. Linear regulators, and more concretely, low-dropout linear regulators, are an essential block in any power management system, able to generate precise and extremely-stable low-noise biasing voltages what make them the ideal choice for extremely biasing-sensitive circuits such as analog or radio-frequency systems. In addition to this, low-dropout linear regulators can be completely integrated without needing any external device, what translates to expenses and area savings. For all these reasons, low-dropout linear regulators have been lately acquiring extensive attention from the scientific community. However, those circuits also have some disadvantages, indeed, the maximum theoretical efficiency that can be achieved though low-dropout linear regulators is lower than switched capacitor or inductor-based solutions efficiency. In addition to this, as internal compensation is required, the system’s dominant pole is given by an internal node, making the non-dominant pole to be fixed by the charge. This leads to a great stability concern as charge variations translate to a frequency displacement of the non-dominant pole that degrades the whole system phase margin. In accordance with previously described issues, this research has been focused on the study of minimum-quiescent consumption internally compensated low-dropout linear regulators (LDO). The first objective of this research is the proposal of low-voltage high-performance LDO structures that do not increase quiescent consumption. Thus, the Flipped Voltage Follower cell has been proposed as regulator due to its inherent low output impedance, great stability and simplicity. The second aim of this research has been the proposal of simple compensation schemes that allow full-operation range stability. So that, a classical Miller compensation based scheme where a replica circuit dynamically adjust the charge resistance has been proposed. Finally, in order to minimize quiescent consumption of LDOs regulators without degrading transient response performance, class-AB buffers have been proposed to drive the pass transistor gate. This technique enhances the transient response as it generates high currents during transitions without compromising efficiency.Premio Extraordinario de Doctorado U

Design of a Low Power External Capacitor-Less Low-Dropout Regulator with Gain-Compensated Error Amplifier

This thesis introduces a gain-compensated external capacitor-less low-dropout voltage regulator with total 5.7 uA quiescent current at all load conditions. The two-stage gain-compensated error amplifier is implemented with a cross-couple pair negative resistor to make the LDO achieve higher gain (> 50 dB) with very low bias current (< 1.3 uA). The LDO can achieve 52 dB loop gain at no load condition, 64 dB at 1 mA and 54 dB at 100 mA load. During transients (0 A to 100 mA) the undershoot is optimized to 98.6 mV with 100 ns rising and falling time through a differentiator circuit to boost the LDO’s transient response. The phase margin of the proposed LDO is 55◦ at 1 mA and 79.27◦ at max load (100 mA). Figure of merit (FOM) of this work is 2.79 fs which is very small

A high-speed low-dropout voltage regulator using a compact output driver

Orientadores: Elnatan Chagas Ferreira, Sandro Augusto Pavlik HaddadTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de ComputaçãoResumo: Ao longo dos anos, microcontroladores tornaram-se mais rápidos e mais poderosos em sua capacidade de processamento graças à evolução dos processos de fabricação. Os novos processos CMOS de menores geometrias exigem tolerâncias menores quanto à tensão de ali-mentação. A lógica digital nesses dispositivos exige que o regulador interno forneça uma ten-são de alimentação estável e precisa, muitas vezes sem o auxílio de um capacitor externo de desacoplamento, o que torna o projeto do regulador uma tarefa árdua devido à natureza da carga digital. São milhões de portas lógicas comutando simultaneamente que ocasionam picos de corrente que podem atingir dezenas de vezes o valor médio do consumo de corrente. Como resultado, o regulador interno deve ser projetado para atender a esse perfil de carga, especial-mente durante as transições de modos de operação. Em outras palavras, quando o microcon-trolador sai de um modo de ultrabaixo consumo (de poucos microampères) para outro modo de operação de alto consumo de potência (dezenas ou centenas de miliampères) e vice-versa. Esse trabalho apresenta a implementação de um regulador LDO (low dropout) utilizan-do um dispositivo de saída NMOS que não sofre de problemas de estabilidade em altas fre-quências. A nova topologia alcança redução de área de silício significativa no estágio de saída e resposta transitória muito rápida para transições agressivas de carga, sem a necessidade de capacitor externo. Um protótipo do circuito proposto foi implementado em tecnologia CMOS split gate TFS (Thin Film Storage) de 90 nm. O silício foi encapsulado em QFP64 e avaliado em labora-tório nas dependências da NXP Semiconductors Brasil. Outra versão do circuito, em processo CMOS 55 nm, já está em produção, foi caracterizado e qualificado em ambiente automotivo. As medidas em laboratório demonstraram que o novo circuito responde extremamente rápido aos transientes de carga na versão fabricada em tecnologia CMOS 90 nm. Isso o torna apropri-ado para aplicações em microcontroladores (cargas predominantemente digitais). Na versão fabricada em 55 nm, mais de uma centena de peças foram medidas em pro-cesso (split lots) e temperatura e serviram para demonstrar que o circuito pode ser projetado também para aplicações focando baixo consumo energiaAbstract: Modern power management System-on-a-Chip (SoC) design demands for fully integrat-ed solutions in order to decrease certain costly features such as the total chip area and the power consumption while maintaining or increasing the regulator response during aggressive load variations. Low-Dropout (LDO) voltage regulators, as power management devices, must comply with these recent technological and industrial trends. On-chip embedded LDO voltage regulators have to deliver stable and accurate local supply voltages to digital circuits that draw large and fast slew-rate current peaks, characteris-tics that are difficult to implement when off-chip inductors and capacitors are not used. The structure and frequency compensation scheme of classical LDO regulators, especially with low-voltage designs, present a trade-off between stability and transient response of the LDO regulator. To improve load regulation under large and fast load variations in linear regulators, it is necessary to employ large area output drivers. Thus, besides stability issues, another diffi-culty in designing LDOs is to create a compact driver with good load regulation and a fast transient response under large load variations. This manuscript presents a novel topology of a capacitor-free CMOS LDO regulator utilizing a compact NMOS output driver. The new output driver cell achieves low voltage ripple and very fast transient response under large load steps with a small silicone area. The circuit has been implemented in a 90 nm CMOS process technology. Silicon results demonstrated a transient loop response faster than 30 ns to a load variation of four orders of magnitude. Another version of the circuit has been implemented in a 55 nm CMOS technology. Alt-hough primarily targeted to attain low power requirements, this version has been qualified to meet industry standard automotive specifications and is currently in production as part of the Power Management Controller (PMC) block integrated within a family of MCUs used in au-tomotive and industrial powertrainDoutoradoEletrônica, Microeletrônica e OptoeletrônicaDoutor em Engenharia Elétric

Design of a Low Power External Capacitor-Less Low-Dropout Regulator with Gain-Compensated Error Amplifier

This thesis introduces a gain-compensated external capacitor-less low-dropout voltage regulator with total 5.7 uA quiescent current at all load conditions. The two-stage gain-compensated error amplifier is implemented with a cross-couple pair negative resistor to make the LDO achieve higher gain (> 50 dB) with very low bias current (< 1.3 uA). The LDO can achieve 52 dB loop gain at no load condition, 64 dB at 1 mA and 54 dB at 100 mA load. During transients (0 A to 100 mA) the undershoot is optimized to 98.6 mV with 100 ns rising and falling time through a differentiator circuit to boost the LDO’s transient response. The phase margin of the proposed LDO is 55◦ at 1 mA and 79.27◦ at max load (100 mA). Figure of merit (FOM) of this work is 2.79 fs which is very small

Modeling, Design and Optimization of IC Power Delivery with On-Chip Regulation

As IC technology continues to follow the Moore’s Law, IC designers have been constantly challenged with power delivery issues. While useful power must be reliably delivered to the on-die functional circuits to fulfill the desired functionality and performance, additional power overheads arise due to the loss associated with voltage conversion and parasitic resistance in the metal wires. Hence, one of the key IC power delivery design challenges is to develop voltage conversion/regulation circuits and the corresponding design strategies to provide a guaranteed level of power integrity while achieving high power efficiency and low area overhead. On-chip voltage regulation, a significant ongoing design trend, offers appealing active supply noise suppression close to the loads and is well positioned to address many power delivery challenges. However, to realize the full potential of on-chip voltage regulation requires systemic optimization of and tradeoffs among settling time, steady-state error, power supply noise, power efficiency, stability and area overhead, which are the key focuses of this dissertation. First, we develop new low-dropout voltage regulators (LDOs) that are well optimized for low power applications. To this end, dropout voltage, bias current and speed are important competing design objectives. This dissertation presents new flipped voltage follower (FVF) based topologies of on-chip voltage regulators that handle ultra-fast load transients in nanoseconds while achieving significant improvement on bias current consumption. An active frequency compensation is embedded to achieve high area efficiency by employing a smaller amount of compensation capacitors, the major silicon area contributor. Furthermore, in one of the proposed topologies an auxiliary digital feedback loop is employed in order to lower quiescent power consumption further. Second, coping with supply noise is becoming increasingly more difficult as design complexity grows, which leads to increased spatial and temporal load heterogeneity, and hence larger voltage variations in a given power domain. Addressing this challenge through a distributed methodology wherein multiple voltage regulators are placed across the same voltage domain is particularly promising. This distributive nature allows for even faster suppression of multiple hot spots by the nearby regulators within the power domain and can significantly boost power integrity. Nevertheless, reasoning about the stability of such distributively regulated power networks becomes rather complicated as a result of complex interactions between multiple active regulators and the large passive subnetwork. Coping with this stability challenge requires new theory and stability-ensuring design practice, as targeted by this dissertation. For the first time, we adopt and develop a hybrid stability framework for large power delivery networks with distributed voltage regulation. This framework is local in the sense that both the checking and assurance of network stability can be dealt with on the basis of each individual voltage regulator, leading to feasible design of large power delivery networks that would be computationally impossible otherwise. Accordingly, we propose a new hybrid stability margin concept, examine its tradeoffs with power efficiency, supply noise and silicon area, and demonstrate the resulted key design implications pertaining to new stability-ensuring LDO circuit design techniques and circuit topologies. Finally, we develop an automated hybrid stability design flow that is computationally efficient and provides a practical guarantee of network stability