Design of low order high OSR discrete time delta-sigma modulator for audio applications

Tato diplomová práce si klade za cíl seznámit čtenáře se základním konceptem a principy jednosmyčkových modulátorů . Diplomová práce ozřejmuje čtenáři problematiku delta-sigma () modulátorů s jednou zpětnovazební smyčkou. Zabývá se základními principy převzorkování u číslicově-analogových převodníků a rozšiřuje je o teorii tvarování spektra šumu. Vycházeje z této teorie jsou navrženy tři jednosmyčkové modulátory, které běží na 1024 OSR jako alternativa k běžně používáným modulátorům vysokých řádů. Modulátory jsou implementovány do FPGA společně s rekonstrukčním filtrem a podpůrnými bloky. Nakonec byl zkonstruován hardwarový prototyp pro vyhodnocení implementace navrženého DAC.This master thesis aims to familiarize the reader with the basic concept and fundamental principles of single-loop modulators. It offers an alternative to a high-order modulators in the form of low-order modulators running at high oversampling rate. Low order modulators have better modulator loop stability, which can be leveraged to get higher noise-shaping power at lower frequencies. A complete digital to analog converter is proposed, mostly implemented in an FPGA. A hardware prototype was built to evaluate the DAC implementation.

Data acquisition techniques based on frequency-encoding applied to capacitive MEMS microphones

Mención Internacional en el título de doctorThis thesis focuses on the development of capacitive sensor readout circuits and data converters based on frequency-encoding. This research has been motivated by the needs of consumer electronics industry, which constantly demands more compact readout circuit for MEMS microphones and other sensors. Nowadays, data acquisition is mainly based on encoding signals in voltage or current domains, which is becoming more challenging in modern deep submicron CMOS technologies. Frequency-encoding is an emerging signal processing technique based on encoding signals in the frequency domain. The key advantage of this approach is that systems can be implemented using mostly-digital circuitry, which benefits from CMOS technology scaling. Frequencyencoding can be used to build phase referenced integrators, which can replace classical integrators (such as switched-capacitor based integrators) in the implementation of efficient analog-to-digital converters and sensor interfaces. The core of the phase referenced integrators studied in this thesis consists of the combination of different oscillator topologies with counters and highly-digital circuitry. This work addresses two related problems: the development of capacitive MEMS sensor readout circuits based on frequency-encoding, and the design and implementation of compact oscillator-based data converters for audio applications. In the first problem, the target is the integration of the MEMS sensor into an oscillator circuit, making the oscillation frequency dependent on the sensor capacitance. This way, the sound can be digitized by measuring the oscillation frequency, using digital circuitry. However, a MEMS microphone is a complex structure on which several parasitic effects can influence the operation of the oscillator. This work presents a feasibility analysis of the integration of a MEMS microphone into different oscillator topologies. The conclusion of this study is that the parasitics of the MEMS limit the performance of the microphone, making it inefficient. In contrast, replacing conventional ADCs with frequency-encoding based ADCs has proven a very efficient solution, which motivates the next problem. In the second problem, the focus is on the development of high-order oscillator-based Sigma-Delta modulators. Firstly, the equivalence between classical integrators and phase referenced integrators has been studied, followed by an overview of state-of-art oscillator-based converters. Then, a procedure to replace classical integrators by phase referenced integrators is presented, including a design example of a second-order oscillator based Sigma-Delta modulator. Subsequently, the main circuit impairments that limit the performance of this kind of implementations, such as phase noise, jitter or metastability, are described. This thesis also presents a methodology to evaluate the impact of phase noise and distortion in oscillator-based systems. The proposed method is based on periodic steady-state analysis, which allows the rapid estimation of the system dynamic range without resorting to transient simulations. In addition, a novel technique to analyze the impact of clock jitter in Sigma-Delta modulators is described. Two integrated circuits have been implemented in 0.13 μm CMOS technology to demonstrate the feasibility of high-order oscillator-based Sigma-Delta modulators. Both chips have been designed to feature secondorder noise shaping using only oscillators and digital circuitry. The first testchip shows a malfunction in the digital circuitry due to the complexity of the multi-bit counters. The second chip, implemented using single-bit counters for simplicity, shows second-order noise shaping and reaches 103 dB-A of dynamic range in the audio bandwidth, occupying only 0.04 mm2.Esta tesis se centra en el desarrollo de conversores de datos e interfaces para sensores capacitivos basados en codificación en frecuencia. Esta investigación está motivada por las necesidades de la industria, que constantemente demanda reducir el tamaño de este tipo de circuitos. Hoy en día, la adquisición de datos está basada principalmente en la codificación de señales en tensión o en corriente. Sin embargo, la implementación de este tipo de soluciones en tecnologías CMOS nanométricas presenta varias dificultades. La codificación de frecuencia es una técnica emergente en el procesado de señales basada en codificar señales en el dominio de la frecuencia. La principal ventaja de esta alternativa es que los sistemas pueden implementarse usando circuitos mayoritariamente digitales, los cuales se benefician de los avances de la tecnología CMOS. La codificación en frecuencia puede emplearse para construir integradores referidos a la fase, que pueden reemplazar a los integradores clásicos (como los basados en capacidades conmutadas) en la implementación de conversores analógico-digital e interfaces de sensores. Los integradores referidos a la fase estudiados en esta tesis consisten en la combinación de diferentes topologías de osciladores con contadores y circuitos principalmente digitales. Este trabajo aborda dos cuestiones relacionadas: el desarrollo de circuitos de lectura para sensores MEMS capacitivos basados en codificación temporal, y el diseño e implementación de conversores de datos compactos para aplicaciones de audio basados en osciladores. En el primer caso, el objetivo es la integración de un sensor MEMS en un oscilador, haciendo que la frecuencia de oscilación depe capacidad del sensor. De esta forma, el sonido puede ser digitalizado midiendo la frecuencia de oscilación, lo cual puede realizarse usando circuitos en su mayor parte digitales. Sin embargo, un micrófono MEMS es una estructura compleja en la que múltiples efectos parasíticos pueden alterar el correcto funcionamiento del oscilador. Este trabajo presenta un análisis de la viabilidad de integrar un micrófono MEMS en diferentes topologías de oscilador. La conclusión de este estudio es que los parasíticos del MEMS limitan el rendimiento del micrófono, causando que esta solución no sea eficiente. En cambio, la implementación de conversores analógico-digitales basados en codificación en frecuencia ha demostrado ser una alternativa muy eficiente, lo cual motiva el estudio del siguiente problema. La segunda cuestión está centrada en el desarrollo de moduladores Sigma-Delta de alto orden basados en osciladores. En primer lugar se ha estudiado la equivalencia entre los integradores clásicos y los integradores referidos a la fase, seguido de una descripción de los conversores basados en osciladores publicados en los últimos años. A continuación se presenta un procedimiento para reemplazar integradores clásicos por integradores referidos a la fase, incluyendo un ejemplo de diseño de un modulador Sigma-Delta de segundo orden basado en osciladores. Posteriormente se describen los principales problemas que limitan el rendimiento de este tipo de sistemas, como el ruido de fase, el jitter o la metaestabilidad. Esta tesis también presenta un nuevo método para evaluar el impacto del ruido de fase y de la distorsión en sistemas basados en osciladores. El método propuesto está basado en simulaciones PSS, las cuales permiten la rápida estimación del rango dinámico del sistema sin necesidad de recurrir a simulaciones temporales. Además, este trabajo describe una nueva técnica para analizar el impacto del jitter de reloj en moduladores Sigma-Delta. En esta tesis se han implementado dos circuitos integrados en tecnología CMOS de 0.13 μm, con el fin de demostrar la viabilidad de los moduladores Sigma-Delta de alto orden basados en osciladores. Ambos chips han sido diseñados para producir conformación espectral de ruido de segundo orden, usando únicamente osciladores y circuitos mayoritariamente digitales. El primer chip ha mostrado un error en el funcionamiento de los circuitos digitales debido a la complejidad de las estructuras multi-bit utilizadas. El segundo chip, implementado usando contadores de un solo bit con el fin de simplificar el sistema, consigue conformación espectral de ruido de segundo orden y alcanza 103 dB-A de rango dinámico en el ancho de banda del audio, ocupando solo 0.04 mm2.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Georges G.E. Gielen.- Secretario: José Manuel de la Rosa.- Vocal: Ana Rus

Design and characterization of a low voltage CMOS ASIC for medical instrumentation

The acquisition of biomedical signals requires analogue to digital converters of high resolution, low voltage of power and low consumption. The solution for this need is the use of new sigma delta conversion architectures such as the one tested in this Bachelor Thesis. This work covers the design of the instrumentation necessary for the operation of Application-Specific Integrated Circuit Sigma Delta Analog-to-Digital Converter (ASIC ADC) that is already manufactured and its integration into a Printed Circuit Board (PCB). It also includes the development of the necessary software that facilitates the accomplishment of the necessary tests and the analysis of the data that will allow to characterize the operation of the fabricated prototype. Finally, the results and conclusions of the project will be described. The ASIC to be tested in this Bachelor Thesis consists of a180-nm Complementary Metal-Oxide Semiconductor (CMOS) bandpass ADC developed to fulfil the specifications of a fully-integrated receiver for Magnetic Resonance Imaging (MRI). Integrating an integrated CMOS receiver into a single chip will help improve image quality by avoiding the use of many coaxial cables that are used to connect the Radio Frequency (RF) coils to the scanning hardware. The proposal made is a very simple Low-IF receiver characteristics in which a continuous time Low-IF bandpass ADC is the most efficient architecture. The circuit in continuous time replaces the classic filter only thus, an anti-alias filter would be necessary. In addition, the bandpass filter assists in the attenuation of the quantization noise in the bandwidth of interest, while at the same time the stability of the system is easily achieved due to the selected Low-IF.Ingeniería Biomédic

Novas arquiteturas para transmissores digitais flexíveis e de banda larga

Next generation of wireless communication (5G) devices must achieve higher data rates, lower power consumption and better coverage by making a more efficient use of the RF spectrum and adopting highly exible radio architectures. To meet these requirements, the development of new radio devices will be far more complex and challenging than their predecessors. The future of radio communications have a twofold evolution, being one the low power consumption and the other the adaptability and intelligent use of the available resources. Conventional approaches for the radio physical layer are not capable to cope with the new demand for multi-band, multi-standard radio signals and present an inefficient and expensive solution for simultaneous transmission of multiple and heterogeneous radio signals. Digital radio transmitters have been presented as a solution for a newer and more exible architecture for future radios. All-digital transmitters use a completely digital implementation of the entire radio datapath from the baseband processing to the digital RF up-conversion. This concept bene ts from the use of highly integrated hardware together with a strong radio digitalization, motivated by the exibility and high performance from cognitive and software defi ned radio. However, such devices are still far from a massive deployment in most of communication scenarios due to some limiting factors that hinder their use. This PhD thesis aims to the development of novel radio architectures and ideas based on all-digital transmitters capable of improving the adaptability and use intelligently the available resources for software de ned and cognitive radio systems. The focus of this thesis is on the improvement of some of the common limitations for all-digital transmitters such as power efficiency, bandwidth, noise-shaping and exibility while using efficient and adaptable digital architectures. In the initial part of the thesis a review of the state-of-the-art is presented showing the most common digital transmitter architectures as well as their major bene ts and key limitations. A comparative analysis of such architectures is made considering their power and spectral efficiency, exibility, performance and cost. Following this initial analysis, the work developed on the course of this PhD is presented and discussed. The initial focus is on the improvement of all-digital transmitters bandwidth trough the study and use of parallel processing techniques capable of greatly improve common bandwidth values presented in the state-of-the-art. The presented work has resulted in several publications where FPGA-based architectures use parallel digital processing techniques to improve the system's bandwidth by a factor higher than 10. Other fundamental contribution of this thesis is focused on the pulsedtransmitters coding efficiency. In this section of the thesis, a method is presented showing the reduction of the quantization noise created by low amplitude resolution digital transmitters using multiple combined pulsedtransmitters to cancel the noise in speci c frequencies. This work has resulted in two main publications that showed how to increase the coding efficiency of the pulse-transmitters as well as the overall efficiency of the transmission system. Lastly, new-noise shaping methods are presented in order to develop new and more exible architectures for all-digital transmitters. The methods presented use new quantization processes that allow for the shaping of the quantization noise produced in pulsed-transmitters while using very simple and adaptable architectures. With these new techniques, it is possible to adjust the noise frequency distribution and deliberately change the noise shape in order to change some of the transmitter's characteristics such as central frequency or bandwidth. The work presented on this thesis has shown promising improvements to the all-digital transmitters' state-of-the-art, either in simulations and laboratory prototype measurements. It has contributed to advance the state-of-the-art in agile and power efficient all-digital RF transmitters with multi-mode and multi-channel capabilities and the improvement of the transceiver's bandwidth enabling the development of true software de ned and cognitive radio systemsA próxima geração de comunicações sem os (5G) exigirá taxas de transmissão mais elevadas, maior efi ciência energética e uma melhor cobertura fazendo um uso mais efi ciente do espectro de radiofrequência e adotando o uso de arquiteturas rádio mais flexíveis. Para cumprir tais requisitos, o desenvolvimento de novos dispositivos rádio será substancialmente mais complexo do que nas gerações anteriores. O futuro das comunicações rádio depende maioritariamente de dois fatores; o baixo consumo de potência e o uso inteligente dos recursos e tecnologias disponíveis. As abordagens convencionais para a camada física dos sistemas rádio não são as mais adequadas para lidar com a necessidade de dispositivos multi-banda e que usem múltiplos standards, por serem soluções inefi cientes e demasiado caras para esse efeito. Os transmissores rádio completamente digitais têm vindo a ser apresentados na literatura como uma solução inovadora e mais flexível para a implementação dos futuros sistemas de rádio. Os transmissores completamente digitais apresentam uma implementação da cadeia de processamento rádio, desde a banda-base até à conversão para RF, completamente constituída por lógica digital. Este conceito tira partido da vasta integração alcançada nas arquiteturas digitais, juntamente com a flexibilidade proveniente da digitalização das arquiteturas rádio que já se encontra em curso com a evolução dos rádios cognitivos e definidos por software. No entanto, devido a algumas limitações inerentes à tecnologia, este tipo de transmissores ainda não é amplamente utilizado na maioria dos sistemas. Esta tese de doutoramento propõe e avalia novas arquiteturas para transmissores completamente digitais, bem como novas técnicas de processamento de sinal que possam beneficiar das tecnologias de implementação existentes (e.g. FPGAs) por forma a construir novos transmissores digitais de forma eficiente e flexível. O objetivo desta tese é reduzir as limitações atuais ainda presentes neste tipo de transmissores, nomeadamente as relacionadas com a eficiência, largura de banda, cancelamento de ruído e falta de flexibilidade. Na parte inicial desta tese é realizada a revisão do estado da arte das diversas topologias de transmissores digitais bem como as suas principais vantagens e limitações técnicas. É também feita uma análise comparativa das diversas técnicas apresentadas em termos da sua eficiência energética, flexibilidade, desempenho e custo. De seguida, é apresentado o trabalho desenvolvido no contexto desta tese de doutoramento, seguindo-se uma discussão focada na resolução das atuais limitações deste tipo de transmissores. A primeira parte foca-se no uso de técnicas de processamento paralelo de sinal, por forma a suportar sinais de largura de banda mais elevada que os reportados no atual estado da arte. O trabalho desenvolvido e publicado baseia-se no uso de arquiteturas implementadas em FPGA que contribuíram para um aumento da largura de banda num fator de aproximadamente dez vezes. Outra das contribuições fundamentais desta tese consiste no aumento da eficiência do sistema através da melhoria da eficiência de codificação do sinal pulsado produzido. Com base no uso de múltiplos transmissores pulsados, e apresentado um esquema de combinação construtiva e destrutiva de sinais para a redução do ruído de quantização proveniente das técnicas de processamento de sinal pulsado usadas. Este trabalho resultou em duas importantes publicações que mostram que a melhoria da eficiência de codificação do sinal pode ser utilizada de forma a obter uma maior eficiência energética do transmissor. Por ultimo, são apresentadas diversas técnicas para a conversão dos sinais banda-base em sinais RF pulsados. As propostas apresentadas permitem o uso de uma arquitetura de hardware simplista, mas configurável por software, o que a torna bastante flexível. Com o uso desta arquitetura e possível alterar em pleno funcionamento a frequência central bem como a largura de banda e resposta do conversor pulsado. O trabalho apresentado nesta tese demonstra alguns dos melhoramentos no estado da arte para transmissores r adio completamente digitais, baseando os resultados obtidos não apenas em simulações mas também na implementação e medidas realizadas sobre protótipos laboratoriais. O trabalho desenvolvido no âmbito desta tese contribuiu com avanços na implementação de transmissores ageis, eficientes, com maior largura de banda e capazes de transmissão em múltiplas bandas com recurso a múltiplos protocolos, abrindo caminho para o desenvolvimento de novos rádios cognitivos e definidos por softwareFCT, FSEPrograma Doutoral em Engenharia Eletrotécnic

Design techniques for clocking high performance signaling systems

Scaling of CMOS technology has progressed relentlessly for the past several decades. In order for this unprecedented scaling to benefit the performance of large digital systems, the communication bandwidth between integrated circuits (ICs) must scale accordingly. However, interconnect technology does not scale as aggressively, making communication between chips the major bottleneck in overall system performance. In addition, supply voltage scaling, increasing device leakage, and increased noise make existing signaling circuits inefficient and difficult to scale. In this thesis, both analog and digital enhancement techniques to mitigate scaling related issues and improve the performance of building blocks used in high- speed signaling systems are discussed. A digital-to-phase converter (DPC) with a resolution better than 100 femto-second resolution, a hybrid analog/digital clock and data recovery (CDR) architecture that improves the tracking range of tra- ditional CDRs by an order of magnitude, and a digital CDR architecture that obviates the need for the charge pump and the large area occupying loop filter, while achieving error-free operation are presented. Measured results obtained from the prototype chips are presented to illustrate the proposed design techniques.Keywords: CDR, PL

Analysis of Current Conveyor based Switched Capacitor Circuits for Application in ∆Σ Modulators

The reduction in supply voltage, loss of dynamic range and increased noise prevent the analog circuits from taking advantage of advanced technologies. Therefore the trend is to move all signal processing tasks to digital domain where advantages of technology scaling can be used. Due to this, there exists a need for data converters with large signal bandwidths, higher speeds and greater dynamic range to act as an interface between real world analog and digital signals. The Delta Sigma (∆Σ) modulator is a data converter that makes use of large sampling rates and noise shaping techniques to achieve high resolution in the band of interest. The modulator consists of analog integrators and comparators which create a modulated digital bit stream whose average represents the input value. Due to their simplicity, they are popular in narrow band receivers, medical and sensor applications. However Operational Amplifiers (Op-Amps) or Operational Transconductance Amplifiers (OTAs), which are commonly used in data converters, present a bottleneck. Due to low supply voltages, designers rely on folded cascode, multistage cascade and bulk driven topologies for their designs. Although the two stage or multistage cascade topologies offer good gain and bandwidth, they suffer from stability problems due to multiple stages and feedback requiring large compensation capacitors. Therefore other low voltage Switched-Capacitor (SC) circuit techniques were developed to overcome these problems, based on inverters, comparators and unity gain buffers. In this thesis we present an alternative approach to design of ∆Σ modulators using Second Generation Current Conveyors (CCIIs). The important feature of these modulators is the replacement of the traditional Op-Amp based SC integrators with CCII based SC integrators. The main design issues such as the effect of the non-idealities in the CCIIs are considered in the operation of SC circuits and solutions are proposed to cancel them. Design tradeoffs and guidelines for various components of the circuit are presented through analysis of existing and the proposed SC circuits. A two step adaptive calibration technique is presented which uses few additional components to measure the integrator input output characteristic and linearize it for providing optimum performance over a wide range of sampling frequencies while maintaining low power and area. The presented CCII integrator and calibration circuit are used in the design of a 4th order (2-2 cascade) ∆Σ modulator which has been fabricated in UMC 90nm/1V technology through Europractice. Experimental values for Signal to Noise+Distortion Ratio (SNDR), Dynamic Range (DR) and Figure Of Merit (FOM) show that the modulator can compete with state of art reconfigurable Discrete-Time (DT) architectures while using lower gain stages and less design complexity

Design and implementation of generalized topologies of time-interleaved variable bandpass Σ−Δ modulators

In this thesis, novel analog-to-digital and digital-to-analog generalized time-interleaved variable bandpass sigma-delta modulators are designed, analysed, evaluated and implemented that are suitable for high performance data conversion for a broad-spectrum of applications. These generalized time-interleaved variable bandpass sigma-delta modulators can perform noise-shaping for any centre frequency from DC to Nyquist. The proposed topologies are well-suited for Butterworth, Chebyshev, inverse-Chebyshev and elliptical filters, where designers have the flexibility of specifying the centre frequency, bandwidth as well as the passband and stopband attenuation parameters. The application of the time-interleaving approach, in combination with these bandpass loop-filters, not only overcomes the limitations that are associated with conventional and mid-band resonator-based bandpass sigma-delta modulators, but also offers an elegant means to increase the conversion bandwidth, thereby relaxing the need to use faster or higher-order sigma-delta modulators. A step-by-step design technique has been developed for the design of time-interleaved variable bandpass sigma-delta modulators. Using this technique, an assortment of lower- and higher-order single- and multi-path generalized A/D variable bandpass sigma-delta modulators were designed, evaluated and compared in terms of their signal-to-noise ratios, hardware complexity, stability, tonality and sensitivity for ideal and non-ideal topologies. Extensive behavioural-level simulations verified that one of the proposed topologies not only used fewer coefficients but also exhibited greater robustness to non-idealties. Furthermore, second-, fourth- and sixth-order single- and multi-path digital variable bandpass digital sigma-delta modulators are designed using this technique. The mathematical modelling and evaluation of tones caused by the finite wordlengths of these digital multi-path sigmadelta modulators, when excited by sinusoidal input signals, are also derived from first principles and verified using simulation and experimental results. The fourth-order digital variable-band sigma-delta modulator topologies are implemented in VHDL and synthesized on Xilinx® SpartanTM-3 Development Kit using fixed-point arithmetic. Circuit outputs were taken via RS232 connection provided on the FPGA board and evaluated using MATLAB routines developed by the author. These routines included the decimation process as well. The experiments undertaken by the author further validated the design methodology presented in the work. In addition, a novel tunable and reconfigurable second-order variable bandpass sigma-delta modulator has been designed and evaluated at the behavioural-level. This topology offers a flexible set of choices for designers and can operate either in single- or dual-mode enabling multi-band implementations on a single digital variable bandpass sigma-delta modulator. This work is also supported by a novel user-friendly design and evaluation tool that has been developed in MATLAB/Simulink that can speed-up the design, evaluation and comparison of analog and digital single-stage and time-interleaved variable bandpass sigma-delta modulators. This tool enables the user to specify the conversion type, topology, loop-filter type, path number and oversampling ratio

Digital Signal Processing Techniques Applied to Radio over Fiber Systems

The dissertation aims to analyze different Radio over Fiber systems for the front-haul applications. Particularly, analog radio over fiber (A-RoF) are simplest and suffer from nonlinearities, therefore, mitigating such nonlinearities through digital predistortion are studied. In particular for the long haul A-RoF links, direct digital predistortion technique (DPDT) is proposed which can be applied to reduce the impairments of A-RoF systems due to the combined effects of frequency chirp of the laser source and chromatic dispersion of the optical channel. Then, indirect learning architecture (ILA) based structures namely memory polynomial (MP), generalized memory polynomial (GMP) and decomposed vector rotation (DVR) models are employed to perform adaptive digital predistortion with low complexities. Distributed feedback (DFB) laser and vertical capacity surface emitting lasers (VCSELs) in combination with single mode/multi-mode fibers have been linearized with different quadrature amplitude modulation (QAM) formats for single and multichannel cases. Finally, a feedback adaptive DPD compensation is proposed. Then, there is still a possibility to exploit the other realizations of RoF namely digital radio over fiber (D-RoF) system where signal is digitized and transmits the digitized bit streams via digital optical communication links. The proposed solution is robust and immune to nonlinearities up-to 70 km of link length. Lastly, in light of disadvantages coming from A-RoF and D-RoF, it is still possible to take only the advantages from both methods and implement a more recent form knows as Sigma Delta Radio over Fiber (S-DRoF) system. Second Order Sigma Delta Modulator and Multi-stAge-noise-SHaping (MASH) based Sigma Delta Modulator are proposed. The workbench has been evaluated for 20 MHz LTE signal with 256 QAM modulation. Finally, The 6x2 GSa/s sigma delta modulators are realized on FPGA to show a real time demonstration of S-DRoF system. The demonstration shows that S-DRoF is a competitive competitor for 5G sub-6GHz band applications