Design guidelines towards compact litho-friendly regular cells

Preprin

Regular cell design approach considering lithography-induced process variations

The deployment delays for EUVL, forces IC design to continue using 193nm wavelength lithography with innovative and costly techniques in order to faithfully print sub-wavelength features and combat lithography induced process variations. The effect of the lithography gap in current and upcoming technologies is to cause severe distortions due to optical diffraction in the printed patterns and thus degrading manufacturing yield. Therefore, a paradigm shift in layout design is mandatory towards more regular litho-friendly cell designs in order to improve line pattern resolution. However, it is still unclear the amount of layout regularity that can be introduced and how to measure the benefits and weaknesses of regular layouts. This dissertation is focused on searching the degree of layout regularity necessary to combat lithography variability and outperform the layout quality of a design. The main contributions that have been addressed to accomplish this objective are: (1) the definition of several layout design guidelines to mitigate lithography variability; (2) the proposal of a parametric yield estimation model to evaluate the lithography impact on layout design; (3) the development of a global Layout Quality Metric (LQM) including a Regularity Metric (RM) to capture the degree of layout regularity of a layout implementation and; (4) the creation of different layout architectures exploiting the benefits of layout regularity to outperform line-pattern resolution, referred as Adaptive Lithography Aware Regular Cell Designs (ALARCs). The first part of this thesis provides several regular layout design guidelines derived from lithography simulations so that several important lithography related variation sources are minimized. Moreover, a design level methodology, referred as gate biasing, is proposed to overcome systematic layout dependent variations, across-field variations and the non-rectilinear gate effect (NRG) applied to regular fabrics by properly configuring the drawn transistor channel length. The second part of this dissertation proposes a lithography yield estimation model to predict the amount of lithography distortion expected in a printed layout due to lithography hotspots with a reduced set of lithography simulations. An efficient lithography hotspot framework to identify the different layout pattern configurations, simplify them to ease the pattern analysis and classify them according to the lithography degradation predicted using lithography simulations is presented. The yield model is calibrated with delay measurements of a reduced set of identical test circuits implemented in a CMOS 40nm technology and thus actual silicon data is utilized to obtain a more realistic yield estimation. The third part of this thesis presents a configurable Layout Quality Metric (LQM) that considering several layout aspects provides a global evaluation of a layout design with a single score. The LQM can be leveraged by assigning different weights to each evaluation metric or by modifying the parameters under analysis. The LQM is here configured following two different set of partial metrics. Note that the LQM provides a regularity metric (RM) in order to capture the degree of layout regularity applied in a layout design. Lastly, this thesis presents different ALARC designs for a 40nm technology using different degrees of layout regularity and different area overheads. The quality of the gridded regular templates is demonstrated by automatically creating a library containing 266 cells including combinational and sequential cells and synthesizing several ITC'99 benchmark circuits. Note that the regular cell libraries only presents a 9\% area penalty compared to the 2D standard cell designs used for comparison and thus providing area competitive designs. The layout evaluation of benchmark circuits considering the LQM shows that regular layouts can outperform other 2D standard cell designs depending on the layout implementation.Los continuos retrasos en la implementación de la EUVL, fuerzan que el diseño de IC se realice mediante litografía de longitud de onda de 193 nm con innovadoras y costosas técnicas para poder combatir variaciones de proceso de litografía. La gran diferencia entre la longitud de onda y el tamaño de los patrones causa severas distorsiones debido a la difracción óptica en los patrones impresos y por lo tanto degradando el yield. En consecuencia, es necesario realizar un cambio en el diseño de layouts hacia diseños más regulares para poder mejorar la resolución de los patrones. Sin embargo, todavía no está claro el grado de regularidad que se debe introducir y como medir los beneficios y los perjuicios de los diseños regulares. El objetivo de esta tesis es buscar el grado de regularidad necesario para combatir las variaciones de litografía y mejorar la calidad del layout de un diseño. Las principales contribuciones para conseguirlo son: (1) la definición de diversas reglas de diseño de layout para mitigar las variaciones de litografía; (2) la propuesta de un modelo para estimar el yield paramétrico y así evaluar el impacto de la litografía en el diseño de layout; (3) el diseño de una métrica para analizar la calidad de un layout (LQM) incluyendo una métrica para capturar el grado de regularidad de un diseño (RM) y; (4) la creación de diferentes tipos de layout explotando los beneficios de la regularidad, referidos como Adaptative Lithography Aware Regular Cell Designs (ALARCs). La primera parte de la tesis, propone las diversas reglas de diseño para layouts regulares derivadas de simulaciones de litografía de tal manera que las fuentes de variación de litografía son minimizadas. Además, se propone una metodología de diseño para layouts regulares, referida como "gate biasing" para contrarrestar las variaciones sistemáticas dependientes del layout, las variaciones en la ventana de proceso del sistema litográfico y el efecto de puerta no rectilínea para configurar la longitud del canal del transistor correctamente. La segunda parte de la tesis, detalla el modelo de estimación del yield de litografía para predecir mediante un número reducido de simulaciones de litografía la cantidad de distorsión que se espera en un layout impreso debida a "hotspots". Se propone una eficiente metodología que identifica los distintos patrones de un layout, los simplifica para facilitar el análisis de los patrones y los clasifica en relación a la degradación predecida mediante simulaciones de litografía. El modelo de yield se calibra utilizando medidas de tiempo de un número reducido de idénticos circuitos de test implementados en una tecnología CMOS de 40nm y de esta manera, se utilizan datos de silicio para obtener una estimación realista del yield. La tercera parte de este trabajo, presenta una métrica para medir la calidad del layout (LQM), que considera diversos aspectos para dar una evaluación global de un diseño mediante un único valor. La LQM puede ajustarse mediante la asignación de diferentes pesos para cada métrica de evaluación o modificando los parámetros analizados. La LQM se configura mediante dos conjuntos de medidas diferentes. Además, ésta incluye una métrica de regularidad (RM) para capturar el grado de regularidad que se aplica en un diseño. Finalmente, esta disertación presenta los distintos diseños ALARC para una tecnología de 40nm utilizando diversos grados de regularidad y diferentes impactos en área. La calidad de estos diseños se demuestra creando automáticamente una librería de 266 celdas incluyendo celdas combinacionales y secuenciales y, sintetizando diversos circuitos ITC'99. Las librerías regulares solo presentan un 9% de impacto en área comparado con diseños de celdas estándar 2D y por tanto proponiendo diseños competitivos en área. La evaluación de los circuitos considerando la LQM muestra que los diseños regulares pueden mejorar otros diseños 2D dependiendo de la implementación del layout

An Etching Study for Self-Aligned Double Patterning

A proposed process flow for a complete FinFET etch module is presented as well as experiments to ensure that the target films are etched uniformly with proper rate, selectivity and anisotropy. The proposed process flow was developed at RIT, designed to closely reproduce what the semiconductor industry uses for a Self-Aligned Double Patterning (SADP) process module while advancing RIT\u27s current cleanroom facility capabilities. The etching experiment is proposed such that a sufficient degree of etch endpoint control can be achieved without a spectrophotometer for endpoint detection using the Magnetically Enhanced Reactive Ion Etching (MERIE) system at RIT. Without the proper etch data a number of critical steps would be incredibly difficult to control. Prior to this work across wafer etch non-uniformity was reported to be approximately 10% with a regular rate of 1400-1500A/min. This was improved through various means to a nonuniformity of \u3c 1% and a rate of 2200A/min on average. A way to achieve the mandrel etch and strip using gas ratios of 4:2:1::CF4:CHF3:C2F6 and 4:1::CHF3:C2F6, was derived, respectively

Interconnect Fabric Reconfigurability for Network on Chip

Microprocessor architectures are evolving at a pace greater than ever before. To meet the industry’s stringent power, performance and cost demands there is a rising trend towards building heterogeneous processors with both CPU cores and off-chip components on the same chip. This is known as a System on Chip. These systems show promising solutions including chip interconnects consisting of Network on Chips (NoCs). These NoCs are composed of routers that control traffic, and channels used to connect different components of the chip itself together. Depending on the processor core's type, specifications, and technology used, the NoC fabrics may consume anywhere ranging from 28% to 40% of the total system power. To reduce this significant power consumption, various solutions were proposed targeting CMOS technology. In this work we focus on NoC topology improvements and reconfigurability using novel VeSFET technology. The work deploys tools used to simulate full systems, such as GPGPUSIM, to evaluate the possible performance/power gains of a hybrid CMOS-VeSFET system. This hybrid system includes CMOS core and memory layers, while the NoC layer is made up of VeSFET transistors. This allows for shorter wire lengths between routers and cores, as well as it permits for extra area to include network reconfigurability features. The necessary modifications to build this hybrid system are area changes due to VeSFET additional layer, routing length changes, pipelining changes, and VeSFET technology parameter additions. The tools modifications necessary to include this system are described in further details in this thesis. The gathered data indicates great promise for the hybrid reconfigurable CMOS-VeSFET system over the conventional non-reconfigurable CMOS system. It is demonstrated that the hybrid VeSFET system has both a power decrease of approximately 57.0% and a performance increase of approximately 50.2%

Multiparametric Magnetic Resonance Imaging Artificial Intelligence Pipeline for Oropharyngeal Cancer Radiotherapy Treatment Guidance

Oropharyngeal cancer (OPC) is a widespread disease and one of the few domestic cancers that is rising in incidence. Radiographic images are crucial for assessment of OPC and aid in radiotherapy (RT) treatment. However, RT planning with conventional imaging approaches requires operator-dependent tumor segmentation, which is the primary source of treatment error. Further, OPC expresses differential tumor/node mid-RT response (rapid response) rates, resulting in significant differences between planned and delivered RT dose. Finally, clinical outcomes for OPC patients can also be variable, which warrants the investigation of prognostic models. Multiparametric MRI (mpMRI) techniques that incorporate simultaneous anatomical and functional information coupled to artificial intelligence (AI) approaches could improve clinical decision support for OPC by providing immediately actionable clinical rationale for adaptive RT planning. If tumors could be reproducibly segmented, rapid response could be classified, and prognosis could be reliably determined, overall patient outcomes would be optimized to improve the therapeutic index as a function of more risk-adapted RT volumes. Consequently, there is an unmet need for automated and reproducible imaging which can simultaneously segment tumors and provide predictive value for actionable RT adaptation. This dissertation primarily seeks to explore and optimize image processing, tumor segmentation, and patient outcomes in OPC through a combination of advanced imaging techniques and AI algorithms. In the first specific aim of this dissertation, we develop and evaluate mpMRI pre-processing techniques for use in downstream segmentation, response prediction, and outcome prediction pipelines. Various MRI intensity standardization and registration approaches were systematically compared and benchmarked. Moreover, synthetic image algorithms were developed to decrease MRI scan time in an effort to optimize our AI pipelines. We demonstrated that proper intensity standardization and image registration can improve mpMRI quality for use in AI algorithms, and developed a novel method to decrease mpMRI acquisition time. Subsequently, in the second specific aim of this dissertation, we investigated underlying questions regarding the implementation of RT-related auto-segmentation. Firstly, we quantified interobserver variability for an unprecedented large number of observers for various radiotherapy structures in several disease sites (with a particular emphasis on OPC) using a novel crowdsourcing platform. We then trained an AI algorithm on a series of extant matched mpMRI datasets to segment OPC primary tumors. Moreover, we validated and compared our best model\u27s performance to clinical expert observers. We demonstrated that AI-based mpMRI OPC tumor auto-segmentation offers decreased variability and comparable accuracy to clinical experts, and certain mpMRI input channel combinations could further improve performance. Finally, in the third specific aim of this dissertation, we predicted OPC primary tumor mid-therapy (rapid) treatment response and prognostic outcomes. Using co-registered pre-therapy and mid-therapy primary tumor manual segmentations of OPC patients, we generated and characterized treatment sensitive and treatment resistant pre-RT sub-volumes. These sub-volumes were used to train an AI algorithm to predict individual voxel-wise treatment resistance. Additionally, we developed an AI algorithm to predict OPC patient progression free survival using pre-therapy imaging from an international data science competition (ranking 1st place), and then translated these approaches to mpMRI data. We demonstrated AI models could be used to predict rapid response and prognostic outcomes using pre-therapy imaging, which could help guide treatment adaptation, though further work is needed. In summary, the completion of these aims facilitates the development of an image-guided fully automated OPC clinical decision support tool. The resultant deliverables from this project will positively impact patients by enabling optimized therapeutic interventions in OPC. Future work should consider investigating additional imaging timepoints, imaging modalities, uncertainty quantification, perceptual and ethical considerations, and prospective studies for eventual clinical implementation. A dynamic version of this dissertation is publicly available and assigned a digital object identifier through Figshare (doi: 10.6084/m9.figshare.22141871)

Clay Mineral Transformations after Bentonite/Clayrocks and Heater/Water Interactions from Lab and Large-Scale Tests

This book, “Clay Mineral Transformations after Bentonite/Clayrocks and Heater/Water Interactions from Lab and Large-Scale Tests”, covers a broad range of relevant and interesting topics related to deep geological disposal of nuclear fuels and radioactive waste. Most countries that generate nuclear power have developed radioactive waste management programmes during the last 50 years to emplace long-lived and/or high-level radioactive wastes in a deep underground repository in a suitably chosen host rock formation. The aim is to remove these wastes from the human environment. If a site is properly chosen, a repository system comprising both natural and engineered barriers would provide a high level of protection from the toxic effects of the waste.The 17 papers published in this Special Issue show that bentonites and clayrocks are an essential component of the multi-barrier system ensuring the long-term safety of the final disposal of nuclear waste. The efficiency of such engineered and natural clay barriers relies on their physical and chemical confinement properties, which should be preserved in the long-term

Digital neuromorphic auditory systems

This dissertation presents several digital neuromorphic auditory systems. Neuromorphic systems are capable of running in real-time at a smaller computing cost and consume lower power than on widely available general computers. These auditory systems are considered neuromorphic as they are modelled after computational models of the mammalian auditory pathway and are capable of running on digital hardware, or more specifically on a field-programmable gate array (FPGA). The models introduced are categorised into three parts: a cochlear model, an auditory pitch model, and a functional primary auditory cortical (A1) model. The cochlear model is the primary interface of an input sound signal and transmits the 2D time-frequency representation of the sound to the pitch models as well as to the A1 model. In the pitch model, pitch information is extracted from the sound signal in the form of a fundamental frequency. From the A1 model, timbre information in the form of time-frequency envelope information of the sound signal is extracted. Since the computational auditory models mentioned above are required to be implemented on FPGAs that possess fewer computational resources than general-purpose computers, the algorithms in the models are optimised so that they fit on a single FPGA. The optimisation includes using simplified hardware-implementable signal processing algorithms. Computational resource information of each model on FPGA is extracted to understand the minimum computational resources required to run each model. This information includes the quantity of logic modules, register quantity utilised, and power consumption. Similarity comparisons are also made between the output responses of the computational auditory models on software and hardware using pure tones, chirp signals, frequency-modulated signal, moving ripple signals, and musical signals as input. The limitation of the responses of the models to musical signals at multiple intensity levels is also presented along with the use of an automatic gain control algorithm to alleviate such limitations. With real-world musical signals as their inputs, the responses of the models are also tested using classifiers – the response of the auditory pitch model is used for the classification of monophonic musical notes, and the response of the A1 model is used for the classification of musical instruments with their respective monophonic signals. Classification accuracy results are shown for model output responses on both software and hardware. With the hardware implementable auditory pitch model, the classification score stands at 100% accuracy for musical notes from the 4th and 5th octaves containing 24 classes of notes. With the hardware implementation auditory timbre model, the classification score is 92% accuracy for 12 classes musical instruments. Also presented is the difference in memory requirements of the model output responses on both software and hardware – pitch and timbre responses used for the classification exercises use 24 and 2 times less memory space for hardware than software

Transistor-Level Layout of Integrated Circuits

In this dissertation, we present the toolchain BonnCell and its underlying algorithms. It has been developed in close cooperation with the IBM Corporation and automatically generates the geometry for functional groups of 2 to approximately 50 transistors. Its input consists of a set of transistors, including properties like their sizes and their types, a specification of their connectivity, and parameters to flexibly control the technological framework as well as the algorithms' behavior. Using this data, the tool computes a detailed geometric realization of the circuit as polygonal shapes on 16 layers. To this end, a placement routine configures the transistors and arranges them in the plane, which is the main subject of this thesis. Subsequently, a routing engine determines wires connecting the transistors to ensure the circuit's desired functionality. We propose and analyze a family of algorithms that arranges sets of transistors in the plane such that a multi-criteria target function is optimized. The primary goal is to obtain solutions that are as compact as possible because chip area is a valuable resource in modern techologies. In addition to the core algorithms we formulate variants that handle particularly structured instances in a suitable way. We will show that for 90% of the instances in a representative test bed provided by IBM, BonnCell succeeds to generate fully functional layouts including the placement of the transistors and a routing of their interconnections. Moreover, BonnCell is in wide use within IBM's groups that are concerned with transistor-level layout - a task that has been performed manually before our automation was available. Beyond the processing of isolated test cases, two large-scale examples for applications of the tool in the industry will be presented: On the one hand the initial design phase of a large SRAM unit required only half of the expected 3 month period, on the other hand BonnCell could provide valuable input aiding central decisions in the early concept phase of the new 14 nm technology generation