1,534 research outputs found
The Nyquist criterion: a useful tool for the robust design of continuous-time ÎŁÎ modulators
This paper introduces a figure of merit for the robustness of continuous-time sigma-delta modulators. It is based on the Nyquist criterion for the equivalent discrete-time (DT) loop filter. It is shown how continuous-time modulators can be designed by optimizing this figure of merit. This way modulators with increased robustness against variations in the noise-transfer function (NTF) parameters are obtained. This is particularly useful for constrained systems, where the system order exceeds the number of design parameters. This situation occurs for example due to the effect of excess loop delay (ELD) or finite gain bandwidth (GBW) of the opamps. Additionally, it is shown that the optimization is equivalent to the minimization of H_infinity, the maximum out-of-band gain of the NTF. This explains why conventional design strategies that are based on H_infinity, such as Schreierâs approach, provide quite robust modulator designs in the case of unconstrained architectures
Multirate cascaded discrete-time low-pass ÎÎŁ modulator for GSM/Bluetooth/UMTS
This paper shows that multirate processing in a cascaded discrete-time ÎÎŁ modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time ÎÎŁ modulator by its adaptibility with the sampling frequency. The power reduction can be achieved by relaxing the sampling speed of the first stage and increasing it appropriately in the second stage. Furthermore, a cascaded ÎÎŁ modulator enables the power efficient implementation of multiple communication standards.@The advantages of multirate cascaded ÎÎŁ modulators are demonstrated by comparing the performance of single-rate and multirate implementations using behavioral-level and circuit-level simulations. This analysis has been further validated with the design of a multirate cascaded triple-mode discrete-time ÎÎŁ modulator. A 2-1 multirate low-pass cascade, with a sampling frequency of 80 MHz in the first stage and 320 MHz in the second stage, meets the requirements for UMTS. The first stage alone is suitable for digitizing Bluetooth and GSM with a sampling frequency of 90 and 50 MHz respectively. This multimode ÎÎŁ modulator is implemented in a 1.2 V 90 nm CMOS technology with a core area of 0.076 mm2. Measurement results show a dynamic range of 66/77/85 dB for UMTS/ Bluetooth/GSM with a power consumption of 6.8/3.7/3.4 mW. This results in an energy per conversion step of 1.2/0.74/2.86 pJ
Output Filter Aware Optimization of the Noise Shaping Properties of {\Delta}{\Sigma} Modulators via Semi-Definite Programming
The Noise Transfer Function (NTF) of {\Delta}{\Sigma} modulators is typically
designed after the features of the input signal. We suggest that in many
applications, and notably those involving D/D and D/A conversion or actuation,
the NTF should instead be shaped after the properties of the
output/reconstruction filter. To this aim, we propose a framework for optimal
design based on the Kalman-Yakubovich-Popov (KYP) lemma and semi-definite
programming. Some examples illustrate how in practical cases the proposed
strategy can outperform more standard approaches.Comment: 14 pages, 18 figures, journal. Code accompanying the paper is
available at http://pydsm.googlecode.co
Design of sigma-delta modulators for analog-to-digital conversion intensively using passive circuits
This thesis presents the analysis, design implementation and experimental evaluation of passiveactive discrete-time and continuous-time Sigma-Delta (ÎŁÎ) modulators (ÎŁÎMs) analog-todigital converters (ADCs).
Two prototype circuits were manufactured. The first one, a discrete-time 2nd-order ÎŁÎM, was designed in a 130 nm CMOS technology. This prototype confirmed the validity of the ultra incomplete settling (UIS) concept used for implementing the passive integrators. This circuit, clocked at 100 MHz and consuming 298 ÎŒW, achieves DR/SNR/SNDR of 78.2/73.9/72.8 dB, respectively, for a signal bandwidth of 300 kHz. This results in a Walden FoMW of 139.3 fJ/conv.-step and Schreier FoMS of 168 dB.
The final prototype circuit is a highly area and power efficient ÎŁÎM using a combination of a cascaded topology, a continuous-time RC loop filter and switched-capacitor feedback paths. The modulator requires only two low gain stages that are based on differential pairs. A systematic design methodology based on genetic algorithm, was used, which allowed decreasing the circuitâs sensitivity to the circuit componentsâ variations. This continuous-time, 2-1 MASH ÎŁÎM has been designed in a 65 nm CMOS technology and it occupies an area of just 0.027 mm2. Measurement results show that this modulator achieves a peak SNR/SNDR of 76/72.2 dB and DR of 77dB for an input signal bandwidth of 10 MHz, while dissipating 1.57 mW from a 1 V power supply voltage. The ÎŁÎM achieves a Walden FoMW of 23.6 fJ/level and a Schreier FoMS of 175 dB. The innovations proposed in this circuit result, both, in the reduction of the power consumption and of the chip size. To the best of the authorâs knowledge the circuit achieves the lowest Walden FOMW for ÎŁÎMs operating at signal bandwidth from 5 MHz to 50 MHz reported to date
Micromachined vibratory gyroscopes controlled by a high order band-pass sigma delta modulator.
AbstractâThis work reports on the design of novel closed-loop control systems for the sense mode of a vibratory-rate gyroscope based on a high-order sigma-delta modulator (SDM). A low-pass and two distinctive bandpass topologies are derived, and their advantages discussed. So far, most closed-loop force-feedback control systems for these sensors were based on low-pass SDMâs. Usually, the sensing element of a vibratory gyroscope is designed with a high quality factor to increase the sensitivity and, hence, can be treated as a mechanical resonator. Furthermore, the output characteristic of vibratory rate gyroscopes is narrowband amplitude- modulated signal. Therefore, a bandpass M is a more appropriate control strategy for a vibratory gyroscope than a low-pass SDM. Using a high-order bandpass SDM, the control system can adopt a much lower sampling frequency compared with a low-pass SDM while achieving a similar noise floor for a given oversampling ratio (OSR). In addition, a control system based on a high-order bandpass SDM is superior as it not only greatly shapes the quantization noise, but also alleviates tonal behavior, as is often seen in low-order SDM control systems, and has good immunities to fabrication tolerances and parameter mismatch. These properties are investigated in this study at system level
Design and implementation of a wideband sigma delta ADC
Abstract. High-speed and wideband ADCs have become increasingly important in response to the growing demand for high-speed wireless communication services. Continuous time sigma delta modulators (CTÆ©âM), well-known for their oversampling and noise shaping properties, offer a promising solution for low-power and high-speed design in wireless applications.
The objective of this thesis is to design and implement a wideband CTÆ©âM for a global navigation satellite system(GNSS) receiver. The targeted modulator architecture is a 3rdorder single-bit CTÆ©âM, specifically designed to operate within a 15 MHz signal bandwidth. With an oversampling ratio of 25, the ADCâs sampling frequency is set at 768 MHz. The design goal is to achieve a theoretical signal to noise ratio (SNR) of 55 dB.
This thesis focuses on the design and implementation of the CTÆ©âM, building upon the principles of a discrete time Æ©â modulator, and leveraging system-level simulation and formulations. A detailed explanation of the coefficient calculation procedure specific to CTÆ©â modulators is provided, along with a "top-down" design approach that ensures the specified requirements are met. MATLAB scripts for coefficient calculation are also included. To overcome the challenges associated with the implementation of CTÆ©â modulators, particularly excess loop delay and clock jitter sensitivity, this thesis explores two key strategies: the introduction of a delay compensation path and the utilization of a finite impulse response (FIR) feedback DAC. By incorporating a delay compensation path, the stability of the modulator can be ensured and its noise transfer function (NTF) can be restored. Additionally, the integration of an FIR feedback DAC addresses the issue of clock jitter sensitivity, enhancing the overall performance and robustness of the CTÆ©âM.
The CTÆ©âMs employ the cascade of integrators with feed forward (CIFF) and cascade of integrators with feedforward and feedback (CIFF-B) topologies, with a particular emphasis on the CIFF-B configuration using 22nm CMOS technology node and a supply voltage of 0.8 V. Various simulations are performed to validate the modulatorâs performance. The simulation results demonstrate an achievable SNR of 55 dB with a power consumption of 1.36 mW. Furthermore, the adoption of NTF zero optimization techniques enhances the SNR to 62 dB.Laajakaistaisen jatkuva-aikaisen sigma delta-AD-muuntimen suunnittelu ja toteutus. TiivistelmĂ€. Nopeat ja laajakaistaiset AD-muuntimet ovat tulleet entistĂ€ tĂ€rkeĂ€mmiksi nopeiden langattomien kommunikaatiopalvelujen kysynnĂ€n kasvaessa. Jatkuva-aikaiset sigma delta -modulaattorit (CTÆ©âM), joissa kĂ€ytetÀÀn ylinĂ€ytteistystĂ€ ja kohinanmuokkausta, tarjoavat lupaavan ratkaisun matalan tehonkulutuksen ja nopeiden langattomien sovellusten suunnitteluun.
TĂ€mĂ€n työn tarkoituksena on suunnitella ja toteuttaa laajakaistainen jatkuva -aikainen sigma delta -modulaattori satelliittipaikannusjĂ€rjestelmien (GNSS) vastaanottimeen. Arkkitehtuuriltaan modulaattori on kolmannen asteen 1-bittinen CTÆ©âM, jolla on 15MHz:n signaalikaistanleveys. YlinĂ€ytteistyssuhde on 25 ja AD muuntimen nĂ€ytteistystaajuus 768 MHz. Tavoitteena on saavuttaa teoreettinen 55 dB signaalikohinasuhde (SNR).
TĂ€mĂ€ työ keskittyy jatkuva-aikaisen sigma delta -modulaattorin suunnitteluun ja toteutukseen, perustuen diskreettiaikaisen Æ©â-modulaattorin periaatteisiin ja systeemitason simulointiin ja mallitukseen. Jatkuva-aikaisen sigma delta -modulaattorin kertoimien laskentamenetelmĂ€ esitetÀÀn yksityiskohtaisesti, ja vaatimusten tĂ€yttyminen varmistetaan âtop-downâ -suunnitteluperiaatteella. LiitteenĂ€ on kertoimien laskemiseen kĂ€ytetty MATLAB-koodi. Jatkuva-aikaisten sigma delta -modulaattoreiden erityishaasteiden, liian pitkĂ€n silmukkaviiveen ja kellojitterin herkkyyden, voittamiseksi tutkitaan kahta strategiaa, viiveen kompensointipolkua ja FIR takaisinkytkentĂ€ -DA muunninta. Viivekompensointipolkua kĂ€yttĂ€mĂ€llĂ€ modulaattorin stabiilisuus ja kohinansuodatusfunktio saadaan varmistettua ja korjattua. LisĂ€ksi FIR takaisinkytkentĂ€ -DA-muuntimen kĂ€yttö pienentÀÀ kellojitteriherkkyyttĂ€, parantaen jatkuva aikaisen sigma delta -modulaattorin kokonaissuorituskykyĂ€ ja luotettavuutta.
Toteutetuissa jatkuva-aikaisissa sigma delta -modulaattoreissa on kytketty perÀkkÀin integraattoreita myötÀkytkentÀrakenteella (CIFF) ja toisessa sekÀ myötÀ- ettÀ takaisinkytkentÀrakenteella (CIFF-B). PÀÀhuomio on CIFF-B rakenteessa, joka toteutetaan 22nm CMOS prosessissa kÀyttÀen 0.8 voltin kÀyttöjÀnnitettÀ. Suorityskyky varmistetaan erilaisilla simuloinneilla, joiden perusteella 55 dB SNR saavutetaan 1.36 mW tehonkulutuksella. LisÀksi kohinanmuokkausfunktion optimoinnilla SNR saadaan nostettua 62 desibeliin
A novel low-voltage reconfigurable ÎŁÎ modulator for 4G wireless receivers
This paper presents a new adaptable cascade
ÎŁÎ
modulator architecture fo
r low-voltage multi-stan-
dard applications. It uses two reconfiguration strategies:
a programmable global resonation and a variable
loop-filter order. These techniques are properly com-
bined in a novel topology that allows to increase the effec-
tive resolution in a given bandwidth, whereas keeping
relaxed output swing requirements and high robustness
to mismatch and to non-linearities of the amplifiers.
Time-domain simulations incl
uding the main
circuit-level
non-idealities are shown to demonstrate the benefits of
the presented modulator when it is configured to cope
with the requirements of GSM, UMTS, WLAN and
Wi-Max.España, Ministerio de EducaciĂłn y Ciencia TEC2007-67247-C02-01/MICEspaña, Ministerio de InnovaciĂłn, Ciencia y Empresa, Junta de AndalucĂa TIC-253
Design, analysis and evaluation of sigma-delta based beamformers for medical ultrasound imaging applications
The inherent analogue nature of medical ultrasound signals in conjunction with the abundant merits provided by digital image acquisition, together with the increasing use of relatively simple front-end circuitries, have created considerable demand for single-bit beamformers in digital ultrasound imaging systems. Furthermore, the increasing need to design lightweight ultrasound systems with low power consumption and low noise, provide ample justification for development and innovation in the use of single-bit beamformers in ultrasound imaging systems. The overall aim of this research program is to investigate, establish, develop and confirm through a combination of theoretical analysis and detailed simulations, that utilize raw phantom data sets, suitable techniques for the design of simple-to-implement hardware efficient digital ultrasound beamformers to address the requirements for 3D scanners with large channel counts, as well as portable and lightweight ultrasound scanners for point-of-care applications and intravascular imaging systems.
In addition, the stability boundaries of higher-order High-Pass (HP) and Band-Pass (BP) ÎŁâÎ modulators for single- and dual- sinusoidal inputs are determined using quasi-linear modeling together with the describing-function method, to more accurately model the modulator quantizer. The theoretical results are shown to be in good agreement with the simulation results for a variety of input amplitudes, bandwidths, and modulator orders. The proposed mathematical models of the quantizer will immensely help speed up the design of higher order HP and BP ÎŁâÎ modulators to be applicable for digital ultrasound beamformers.
Finally, a user friendly design and performance evaluation tool for LP, BP and HP modulators is developed. This toolbox, which uses various design methodologies and covers an assortment of modulators topologies, is intended to accelerate the design process and evaluation of modulators. This design tool is further developed to enable the design, analysis and evaluation of beamformer structures including the noise analyses of the final B-scan images. Thus, this tool will allow researchers and practitioners to design and verify different reconstruction filters and analyze the results directly on the B-scan ultrasound images thereby saving considerable time and effort
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