Process Optimization and Downscaling of a Single Electron Single Dot Memory

This paper presents the process optimization of a single-electron nanoflash electron memory. Self-aligned single dot memory structures have been fabricated using a wet anisotropic oxidation of a silicon nanowire. One of the main issue was to clarify the process conditions for the dot formation. Based on the process modeling, the influence of various parameters (oxidation temperature, nanowire shape) has been investigated. The necessity of a sharp compromise between these different parameters to ensure the presence of the memory dot has been established. In order to propose an aggressive memory cell, the downscaling of the device has been carefully studied. Scaling rules show that the size of the original device could be reduced by a factor of 2. This point has been previously confirmed by the realization of single-electron memory devices

Study program to improve the open-circuit voltage of low resistivity single crystal silicon solar cells

The results of a 14 month program to improve the open circuit voltage of low resistivity silicon solar cells are described. The approach was based on ion implantation in 0.1- to 10.0-ohm-cm float-zone silicon. As a result of the contract effort, open circuit voltages as high as 645 mV (AMO 25 C) were attained by high dose phosphorus implantation followed by furnace annealing and simultaneous SiO2 growth. One key element was to investigate the effects of bandgap narrowing caused by high doping concentrations in the junction layer. Considerable effort was applied to optimization of implant parameters, selection of furnace annealing techniques, and utilization of pulsed electron beam annealing to minimize thermal process-induced defects in the completed solar cells

OPTIMIZATION OF MULTI-JUNCTION SOLAR CELLS FOR SPACE APPLICATIONS MODELED WITH SILVACO ATLAS

Dual junction solar cells are used in space applications for their high efficiency. In this thesis, we model an indium gallium phosphide/gallium arsenide dual-junction solar cell. The solar cell is modeled using Silvaco ATLAS software. Solar cell layer thicknesses and doping concentrations were varied to find optimum efficiency parameters for the solar cell under a variety of radiation conditions. These radiation conditions mimic the damage done at various orbits around Earth for an arbitrary mission length of 12 years. The optimization process resulted in an improved efficiency of 15.1% to 22.4%.http://archive.org/details/optimizationofmu1094559615Lieutenant, United States NavyApproved for public release; distribution is unlimited

An effective modeling approach for high efficient solar cell using virtual wafer fabrication tools

In order to give a real understanding and realization of all the phenomena occurring inside the photovoltaic cell devices, the development of a reliable simulated model first is also essential. In this paper, a novel method for developing a realistic model of an efficient solar cell is presented. An efficient model of a Dual Junction InGaP/GaAs solar cell having GaAs tunnel diode is prepared and fully simulated using Silvaco VWF/ATLAS code. An optimization of window layer, ARC, BSF etc are also performed incorporating the effect of some of the different parameters on the performance of this model. The major stages of the process are explained and the simulation results are compared with published experimental data to demonstrate the accuracy of our results produced by the model utilizing this technique. For this optimized InGaP/GaAs Dual Junction cell model having 125 nm DLAR on 18 nm InAlP textured window with effective 500 nm InAlGaP bottom BSF , a maximum conversion efficiency of 32.20 % (1 sun) and 36.67 % (1000 suns) is obtained under AM1.5G illumination. The introduction of this modeling technique to the photovoltaic community will prove to be of great importance in aiding in the design and development of advanced solar cells using Silvaco Virtual Wafer Fabrication Tools. When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/2212

Nanowire Zinc Oxide MOSFET Pressure Sensor

Fabrication and characterization of a new kind of pressure sensor using self-assembly Zinc Oxide (ZnO) nanowires on top of the gate of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is presented. Self-assembly ZnO nanowires were fabricated with a diameter of 80 nm and 800 nm height (80:8 aspect ratio) on top of the gate of the MOSFET. The sensor showed a 110% response in the drain current due to pressure, even with the expected piezoresistive response of the silicon device removed from the measurement. The pressure sensor was fabricated through low temperature bottom up ultrahigh aspect ratio ZnO nanowire growth using anodic alumina oxide (AAO) templates. The pressure sensor has two main components: MOSFET and ZnO nanowires. Silicon Dioxide growth, photolithography, dopant diffusion, and aluminum metallization were used to fabricate a basic MOSFET. In the other hand, a combination of aluminum anodization, alumina barrier layer removal, ZnO atomic layer deposition (ALD), and wet etching for nanowire release were optimized to fabricate the sensor on a silicon wafer. The ZnO nanowire fabrication sequence presented is at low temperature making it compatible with CMOS technology

Research on AlGaAs

Issued as Monthly cost status reports [nos. 1-11], Monthly technical progress report, nos. 1-11, and Draft final report, Project no. E-21-60

Development of a Novel Hybrid Multi-Junction Architecture for Silicon Solar Cells

Although existing technology can produce highly efficient solar cells, they remain commercially cost-prohibitive. A low-cost alternative was investigated in this research by developing a novel hybrid multi-junction silicon (HMJ-Si) solar cell architecture through modeling, fabrication, and testing. The architecture consists of stacked silicon solar cells with an air gap between them and was designed with metal grating contacts that exploit interference patterns for light management. The interference patterns were examined in MATLAB and verified using Lumerical FDTD Solutions. Development focused on wafer configuration; diffusion profile; front contact design; optical, electrical, and thermal loss reduction; and efficiency. The architecture was optimized using an unpolished-front, p-type top cell with 128nm of Si3N4, a butterfly front contact, and 400 m grating spaced 900 m apart; a polished-front, n-type bottom cell with 200 m grating spaced 1100 m apart; and both cells having an enhanced back surface field diffusion profile with 500nm silver contacts. Efficiency peaked at 8.42% using a silver-coated wafer in lieu of the bottom cell. The results indicate that the architecture is a viable solar cell design requiring additional research for optimization

높은 전류 구동능력을 가지는 SiGe 나노시트 구조의 터널링 전계효과 트랜지스터

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2021. 2. 박병국.The development of very-large-scale integration (VLSI) technology has continuously demanded smaller devices to achieve high integration density for faster computing speed or higher capacity. However, in the recent complementary-metal-oxide-semiconductor (CMOS) technology, simple downsizing the dimension of metal-oxide-semiconductor field-effect transistor (MOSFET) no longer guarantees the boosting performance of IC chips. In particular, static power consumption is not reduced while device size is decreasing because voltage scaling is slowed down at some point. The increased off-current due to short-channel effect (SCE) of MOSFET is a representative cause of the difficulty in voltage scaling. To overcome these fundamental limits of MOSFET, many researchers have been looking for the next generation of FET device over the last ten years. Tunnel field-effect transistor (TFET) has been intensively studied for its steep switching characteristics. Nevertheless, the poor current drivability of TFET is the most serious obstacle to become competitive device for MOSFET. In this thesis, TFET with high current drivability in which above-mentioned problem is significantly solved is proposed. Vertically-stacked SiGe nanosheet channels are used to boost carrier injection and gate control. The fabrication technique to form highly-condensed SiGe nanosheets is introduced. TFET is fabricated with MOSFET with the same structure in the CMOS-compatible process. Both technology-computer-aided-design (TCAD) simulation and experimental results are utilized to support and examine the advantages of proposed TFET. From the perspective of the single device, the improvement in switching characteristics and current drivability are quantitatively and qualitatively analyzed. In addition, the device performance is compared to the benchmark of previously reported TFET and co-fabricated MOSFET. Through those processes, the feasibility of SiGe nanosheet TFET is verified. It is revealed that the proposed SiGe nanosheet TFET has notable steeper switching and low leakage in the low drive voltage as an alternative to conventional MOSFET.초고밀도 집적회로 기술의 발전은 고집적도 달성을 통해 단위 칩의 연산 속도 및 용량 향상에 기여할 소형의 소자를 끊임없이 요구하고 있다. 하지만 최신의 상보형 금속-산화막-반도체 (CMOS) 기술에서 금속-산화막-반도체 전계 효과 트랜지스터 (MOSFET) 의 단순한 소형화는 더 이상 집적회로의 성능 향상을 보장해 주지 못하고 있다. 특히 소자의 크기가 줄어드는 반면 정적 전력 소모량은 전압 스케일링의 둔화로 인해 감소되지 않고 있는 상황이다. MOSFET의 짧은 채널 효과로 인해 증가된 누설 전류가 전압 스케일링의 어려움을 주는 대표적 원인으로 꼽힌다. 이러한 근본적인 MOSFET의 한계를 극복하기 위하여 지난 10여년간 새로운 단계의 전계 효과 트랜지스터 소자들이 연구되고 있다. 그 중 터널 전계 효과 트랜지스터(TFET)은 그 특유의 우수한 전원 특성으로 각광받아 집중적으로 연구되고 있다. 많은 연구에도 불구하고, TFET의 부족한 전류 구동 능력은 MOSFET의 대체재로 자리매김하는 데 가장 큰 문제점이 되고 있다. 본 학위논문에서는 상기된 문제점을 해결할 수 있는 우수한 전류 구동 능력을 가진 TFET이 제안되었다. 반송자 유입과 게이트 컨트롤을 향상시킬 수 있는 수직 적층된 실리콘저마늄(SiGe) 나노시트 채널이 사용되었다. 또한, 제안된 TFET은 CMOS 기반 공정을 활용하여 MOSFET과 함께 제작되었다. 테크놀로지 컴퓨터 지원 설계(TCAD) 시뮬레이션과 실제 측정 결과를 활용하여 제안된 소자의 우수성을 검증하였다. 단위 CMOS 소자의 관점에서, 전원 특성과 전류 구동 능력의 향상을 정량적, 정성적 방법으로 분석하였다. 그리고, 제작된 소자의 성능을 기존 제작 및 보고된 TFET 및 함께 제작된 MOSSFET과 비교하였다. 이러한 과정을 통해, 실리콘저마늄 나노시트 TFET의 활용 가능성이 입증되었다. 제안된 실리콘저마늄 나노시트 소자는 주목할 만한 전원 특성을 가졌고 저전압 구동 환경에서 한층 더 낮은 누설 전류를 가짐으로써 향후 MOSFET을 대체할만한 충분한 가능성을 보여주었다.Chapter 1 Introduction 1 1.1. Power Crisis of Conventional CMOS Technology 1 1.2. Tunnel Field-Effect Transistor (TFET) 6 1.3. Feasibility and Challenges of TFET 9 1.4. Scope of Thesis 11 Chapter 2 Device Characterization 13 2.1. SiGe Nanosheet TFET 13 2.2. Device Concept 15 2.3. Calibration Procedure for TCAD simulation 17 2.4. Device Verification with TCAD simulation 21 Chapter 3 Device Fabrication 31 3.1. Fabrication Process Flow 31 3.2. Key Processes for SiGe Nanosheet TFET 33 3.2.1. Key Process 1 : SiGe Nanosheet Formation 34 3.2.2. Key Process 2 : Source/Drain Implantation 41 3.2.3. Key Process 3 : High-κ/Metal gate Formation 43 Chapter 4 Results and Discussion 53 4.1. Measurement Results 53 4.2. Analysis of Device Characteristics 56 4.2.1. Improved Factors to Performance in SiGe Nanosheet TFET 56 4.2.2. Performance Comparison with SiGe Nanosheet MOSFET 62 4.3. Performance Evaluation through Benchmarks 64 4.4. Optimization Plan for SiGe nanosheet TFET 66 4.4.1. Improvement of Quality of Gate Dielectric 66 4.4.2. Optimization of Doping Junction at Source 67 Chapter 5 Conclusion 71 Bibliography 73 Abstract in Korean 81 List of Publications 83Docto